*==============================================================
* buffalo.asm - Defines Buffalo-specific addresses of interest,
*    namely addresses of the subroutine jumptable in ROM and
*    the interrupt service routine (ISR) jumptable in RAM.
*    Must be included before your own ORG directives.
*==============================================================
#include "core.asm"			; Defines JUMPSIZE

* Buffalo subroutine jumptable addresses
* Each location in the jump table contains an appropriate JMP instruction.
* To use, just JSR to the jump table address that you want to use.

Buffalo_utljmp_base	org	$ffa0
			
UPCASE	 rmb	JUMPSIZE	; Convert character to uppercase
WCHEK	 rmb	JUMPSIZE	; Test character for whitespace
DCHEK	 rmb	JUMPSIZE	; Check character for delimiter
INITDEV	 rmb	JUMPSIZE	; Initialize I/O device
INPUT	 rmb	JUMPSIZE	; Read I/O device
OUTPUT	 rmb	JUMPSIZE	; Write I/O device
OUTLHLF	 rmb	JUMPSIZE	; Convert left nibble to ASCII and output
OUTRHLF	 rmb	JUMPSIZE	; Convert right nibble to ASCII and output
OUTA	 rmb	JUMPSIZE	; Output ASCII character
OUT1BYT	 rmb	JUMPSIZE	; Convert binary byte to 2 ASCII characters and output
OUT1BSP	 rmb	JUMPSIZE	; Convert binary byte to 2 ASCII characters and output followed by space
OUT2BSP	 rmb	JUMPSIZE	; Convert 2 consecutive binary bytes to 4 ASCII characters and output followed by space
OUTCRLF	 rmb	JUMPSIZE	; Output ASCII carriage return followed by line feed
OUTSTRG	 rmb	JUMPSIZE	; Output ASCII string until end of transmission ($04)
OUTSTRG0 rmb	JUMPSIZE	; Same as OUTSTRG except leading carriage return and line feed is skipped
INCHAR	 rmb	JUMPSIZE	; Input ASCII character and echo back
VECINIT  rmb	JUMPSIZE	; Initialize RAM interrupt vector table

* Buffalo interrupt vector jumptable addresses
* Each location in the jump table contains an appropriate JMP instruction.
* To use, store the address of your ISR at the jumptable address+1.

Buffalo_intjmp_base	org	$00c4

JSCI	rmb	JUMPSIZE	; Serial Communications Interface
JSPI	rmb	JUMPSIZE	; Serial Peripheral Interface
JPAIE	rmb	JUMPSIZE	; Pulse Accumulator input edge
JPAO	rmb	JUMPSIZE	; Pulse Accumulator overflow
JTOF	rmb	JUMPSIZE	; Timer overflow
JTI4C5	rmb	JUMPSIZE	; Timer input capture 4 / output compare 5
JTOC4	rmb	JUMPSIZE	; Timer output compare 4
JTOC3	rmb	JUMPSIZE	; Timer output compare 3
JTOC2	rmb	JUMPSIZE	; Timer output compare 2
JTOC1	rmb	JUMPSIZE	; Timer output compare 1
JTIC3	rmb	JUMPSIZE	; Timer input capture 3
JTIC2	rmb	JUMPSIZE	; Timer input capture 2
JTIC1	rmb	JUMPSIZE	; Timer input capture 1
JRTI	rmb	JUMPSIZE	; Real-time interrupt
JIRQ	rmb	JUMPSIZE	; IRQ pin (maskable)
JXIRQ	rmb	JUMPSIZE	; XIRQ pin (nonmaskable)
JSWI	rmb	JUMPSIZE	; Software Interrupt
JILLOP	rmb	JUMPSIZE	; Illegal opcode trap
JCOP	rmb	JUMPSIZE	; Computer Operating Properly watchdog failure
JCLM	rmb	JUMPSIZE	; Clock monitor failure

* Pseudo-vector addresses in RAM, within the above jumptable entries.
* The +1's are to skip over the JMP instruction opcode.

PVSCI	equ	JSCI+1		; Serial Communications Interface
PVSPI	equ	JSPI+1		; Serial Peripheral Interface
PVPAIE	equ	JPAIE+1		; Pulse Accumulator input edge
PVPAO	equ	JPAO+1		; Pulse Accumulator overflow
PVTOF	equ	JTOF+1		; Timer overflow
PVTI4C5	equ	JTI4C5+1	; Timer input capture 4 / output compare 5
PVTOC4	equ	JTOC4+1		; Timer output compare 4
PVTOC3	equ	JTOC3+1		; Timer output compare 3
PVTOC2	equ	JTOC2+1		; Timer output compare 2
PVTOC1	equ	JTOC1+1		; Timer output compare 1
PVTIC3	equ	JTIC3+1		; Timer input capture 3
PVTIC2	equ	JTIC2+1		; Timer input capture 2
PVTIC1	equ	JTIC1+1		; Timer input capture 1
PVRTI	equ	JRTI+1		; Real-time interrupt
PVIRQ	equ	JIRQ+1		; IRQ pin (maskable)
PVXIRQ	equ	JXIRQ+1		; XIRQ pin (nonmaskable)
PVSWI	equ	JSWI+1		; Software Interrupt
PVILLOP	equ	JILLOP+1	; Illegal opcode trap
PVCOP	equ	JCOP+1		; Computer Operating Properly watchdog failure
PVCLM	equ	JCLM+1		; Clock monitor failure