ADDR B1 B2 B3 B4 F:\chicken\keyint.asm PAGE 1 * keyint.asm - Test circuit for setting IRQ based on keypad #include "registers.asm" ; Declares control registers. rbase EQU $1000 ; Default base . address of HC11 I/O control registers *------------------------------------------------------------ . ---------- * Internal HC11 I/O registers defined as addresses starting . from rbase. *------------------------------------------------------------ . ---------- * Parallel I/O registers. PORTA EQU rbase+$00 ; Port A Data Register res0 EQU rbase+$01 ; Reserved register #0 PIOC EQU rbase+$02 ; Parallel I/O Control . Register PORTC EQU rbase+$03 ; Port C Data Register PORTB EQU rbase+$04 ; Port B Data Register PORTCL EQU rbase+$05 ; Port C Latched Register res1 EQU rbase+$06 ; Reserved register #1 DDRC EQU rbase+$07 ; Port C Data Direction . Register PORTD EQU rbase+$08 ; Port D Data Register DDRD EQU rbase+$09 ; Port D Data Direction . Register PORTE EQU rbase+$0a ; Port E Data Register * Timer system registers. CFORC EQU rbase+$0b ; Timer Compare Force . Register OC1M EQU rbase+$0c ; Output Compare 1 Mask . Register OC1D EQU rbase+$0d ; Output Compare 1 Data . Register TCNTH EQU rbase+$0e ; Timer Counter Register High . (MSB) TCNTL EQU rbase+$0f ; Timer Counter Register Low . (LSB) TIC1H EQU rbase+$10 ; Timer Input Capture 1 . Register High (MSB) TIC1L EQU rbase+$11 ; Timer Input Capture 1 . Register Low (LSB) TIC2H EQU rbase+$12 ; Timer Input Capture 2 . Register High (MSB) TIC2L EQU rbase+$13 ; Timer Input Capture 2 . Register Low (LSB) TIC3H EQU rbase+$14 ; Timer Input Capture 3 . Register High (MSB) TIC3L EQU rbase+$15 ; Timer Input Capture 3 . Register Low (LSB) TOC1H EQU rbase+$16 ; Timer Output Compare 1 . Register High (MSB) TOC1L EQU rbase+$17 ; Timer Output Compare 1 . Register Low (LSB) TOC2H EQU rbase+$18 ; Timer Output Compare 2 . Register High (MSB) TOC2L EQU rbase+$19 ; Timer Output Compare 2 . Register Low (LSB) TOC3H EQU rbase+$1a ; Timer Output Compare 3 . Register High (MSB) ADDR B1 B2 B3 B4 F:\chicken\keyint.asm PAGE 2 TOC3L EQU rbase+$1b ; Timer Output Compare 3 . Register Low (LSB) TOC4H EQU rbase+$1c ; Timer Output Compare 4 . Register High (MSB) TOC4L EQU rbase+$1d ; Timer Output Compare 4 . Register Low (LSB) TI4O5H EQU rbase+$1e ; Timer Input Capture 4/ . Output Compare 5 Register High (MSB) TI4O5L EQU rbase+$1f ; Timer Input Capture 4/ . Output Compare 5 Register Low (LSB) TCTL1 EQU rbase+$20 ; Timer Control Register 1 TCTL2 EQU rbase+$21 ; Timer Control Register 2 TMSK1 EQU rbase+$22 ; Timer Interrupt Mask 1 . Register TFLG1 EQU rbase+$23 ; Timer Interrupt Flag 1 TMSK2 EQU rbase+$24 ; Timer Interrupt Mask 2 . Register TFLG2 EQU rbase+$25 ; Timer Interrupt Flag 2 PACTL EQU rbase+$26 ; Pulse Accumulator Control . Register PACNT EQU rbase+$27 ; Pulse Accumulator Count . Register * Serial Peripheral Interface (SPI) registers. SPCR EQU rbase+$28 ; Serial Peripheral Control . Register SPSR EQU rbase+$29 ; Serial Peripheral Status . Register SPDR EQU rbase+$2a ; Serial Peripheral Data I/O . Register * Serial Communications Interface (SCI) registers. BAUD EQU rbase+$2b ; Baud Rate Register SCCR1 EQU rbase+$2c ; Serial Communications . Control Register 1 SCCR2 EQU rbase+$2d ; Serial Communications . Control Register 2 SCSR EQU rbase+$2e ; Serial Communications . Status Register SCDR EQU rbase+$2f ; Serial Communications Data . Register * Analog-to-Digital (A2D) system registers. ADCTL EQU rbase+$30 ; Analog-to-Digital Control . Status Register ADR1 EQU rbase+$31 ; Analog-to-Digital Results . Register 1 ADR2 EQU rbase+$32 ; Analog-to-Digital Results . Register 2 ADR3 EQU rbase+$33 ; Analog-to-Digital Results . Register 3 ADR4 EQU rbase+$34 ; Analog-to-Digital Results . Register 4 * Miscellaneous control and configuration registers. BPROT EQU rbase+$35 ; Block Protect Register EPROG EQU rbase+$36 ; EPROM Programming Control . Register (711E20 only) res2 EQU rbase+$37 ; Reserved register #2 res3 EQU rbase+$38 ; Reserved register #3 OPTION EQU rbase+$39 ; System Configuration ADDR B1 B2 B3 B4 F:\chicken\keyint.asm PAGE 3 . Options Register COPRST EQU rbase+$3a ; Arm/Reset COP Timer . Circuitry Register PPROG EQU rbase+$3b ; EPROM and EEPROM . Programming Control Register HPRIO EQU rbase+$3c ; Highest Priority I Bit . Interrupt and Miscellaneous Reigster INIT EQU rbase+$3d ; RAM and I/O Mapping . Register res4 EQU rbase+$3e ; Reserved register #4 CONFIG EQU rbase+$3f ; System Configuration . Register *---------------------------------------------------------- * Individual register bits. * See datasheet for full descriptions. (Index on pp.38-43.) * * To use these, use BSET, BCLR, BRSET, BRCLR instructions * on the appropriate register address and with an * appropriate mask (logical OR of bits that you want). *---------------------------------------------------------- *---------------- * Parallel Ports * PORTA - Port A Data Register ($1000) PA7 EQU BIT7 PA6 EQU BIT6 PA5 EQU BIT5 PA4 EQU BIT4 PA3 EQU BIT3 PA2 EQU BIT2 PA1 EQU BIT1 PA0 EQU BIT0 * PIOC - Parallel I/O Control Register ($1002) STAF EQU BIT7 STAI EQU BIT6 CWOM EQU BIT5 HNDS EQU BIT4 OIN EQU BIT3 PLS EQU BIT2 EGA EQU BIT1 INVB EQU BIT0 * PORTC - Port C Data Register ($1003) PC7 EQU BIT7 PC6 EQU BIT6 PC5 EQU BIT5 PC4 EQU BIT4 PC3 EQU BIT3 PC2 EQU BIT2 PC1 EQU BIT1 PC0 EQU BIT0 * PORTB - Port B Data Register ($1004) PB7 EQU BIT7 PB6 EQU BIT6 PB5 EQU BIT5 PB4 EQU BIT4 PB3 EQU BIT3 ADDR B1 B2 B3 B4 F:\chicken\keyint.asm PAGE 4 PB2 EQU BIT2 PB1 EQU BIT0 PB0 EQU BIT0 * PORTCL - Port C Latched Register ($1005) PCL7 EQU BIT7 PCL6 EQU BIT6 PCL5 EQU BIT5 PCL4 EQU BIT4 PCL3 EQU BIT3 PCL2 EQU BIT2 PCL1 EQU BIT1 PCL0 EQU BIT0 * DDRC - Port C Data Direction Register ($1007) DDRC7 EQU BIT7 DDRC6 EQU BIT6 DDRC5 EQU BIT5 DDRC4 EQU BIT4 DDRC3 EQU BIT3 DDRC2 EQU BIT2 DDRC1 EQU BIT1 DDRC0 EQU BIT0 * PORTD - Port D Data Register ($1008) PD5 EQU BIT5 PD4 EQU BIT4 PD3 EQU BIT3 PD2 EQU BIT2 PD1 EQU BIT1 PD0 EQU BIT0 * DDRD - Port D Data Register ($1009) DDRD5 EQU BIT5 DDRD4 EQU BIT4 DDRD3 EQU BIT3 DDRD2 EQU BIT2 DDRD1 EQU BIT1 DDRD0 EQU BIT0 * PORTE - Port E Data Register ($100a) PE7 EQU BIT7 PE6 EQU BIT6 PE5 EQU BIT5 PE4 EQU BIT4 PE3 EQU BIT3 PE2 EQU BIT2 PE1 EQU BIT1 PE0 EQU BIT0 *----------------- * Timer facility * CFORC - Timer Compare Force Register ($100b) FOC1 EQU BIT7 FOC2 EQU BIT6 FOC3 EQU BIT5 FOC4 EQU BIT4 FOC5 EQU BIT3 ADDR B1 B2 B3 B4 F:\chicken\keyint.asm PAGE 5 * OC1M - Output Compare 1 Mask Register ($100c) OC1M7 EQU BIT7 OC1M6 EQU BIT6 OC1M5 EQU BIT5 OC1M4 EQU BIT4 OC1M3 EQU BIT3 * OC1D - Output Compare 1 Data Register ($100d) OC1D7 EQU BIT7 OC1D6 EQU BIT6 OC1D5 EQU BIT5 OC1D4 EQU BIT4 OC1D3 EQU BIT3 * TCTL1 - Timer Control Register 1 ($1020) OM2 EQU BIT7 OL2 EQU BIT6 OM3 EQU BIT5 OL3 EQU BIT4 OM4 EQU BIT3 OL4 EQU BIT2 OM5 EQU BIT1 OL5 EQU BIT0 * TCTL2 - Timer Control Register 2 ($1021) EDG4B EQU BIT7 EDG4A EQU BIT6 EDG1B EQU BIT5 EDG1A EQU BIT4 EDG2B EQU BIT3 EDG2A EQU BIT2 EDG3B EQU BIT1 EDG3A EQU BIT0 * TMSK1 - Timer Interrupt Mask 1 Register ($1022) OC1I EQU BIT7 OC2I EQU BIT6 OC3I EQU BIT5 OC4I EQU BIT4 I4O5I EQU BIT3 IC1I EQU BIT2 IC2I EQU BIT1 IC3I EQU BIT0 * TFLG1 - Timer Interrupt Flag 1 ($1023) OC1F EQU BIT7 OC2F EQU BIT6 OC3F EQU BIT5 OC4F EQU BIT4 I4O5F EQU BIT3 IC1F EQU BIT2 IC2F EQU BIT1 IC3F EQU BIT0 * TMSK2 - Timer Interrupt Mask 2 Register ($1024) TOI EQU BIT7 RTII EQU BIT6 ADDR B1 B2 B3 B4 F:\chicken\keyint.asm PAGE 6 PAOVI EQU BIT5 PAII EQU BIT4 PR1 EQU BIT1 PR0 EQU BIT0 * TFLG2 - Timer Interrupt Flag 2 ($1025) TOF EQU BIT7 RTIF EQU BIT6 PAOVF EQU BIT5 PAIF EQU BIT4 * PACTL - Pulse Accumulator Control Register ($1026) DDRA7 EQU BIT7 PAEN EQU BIT6 PAMOD EQU BIT5 PEDGE EQU BIT4 DDRA3 EQU BIT3 I4O5 EQU BIT2 RTR1 EQU BIT1 RTR0 EQU BIT0 *----------------------------------- * Serial Peripheral Interface (SPI) * SPCR - Serial Peripheral Control Register ($1028) SPIE EQU BIT7 SPE EQU BIT6 DWOM EQU BIT5 MSTR EQU BIT4 CPOL EQU BIT3 CPHA EQU BIT2 SPR1 EQU BIT1 SPR0 EQU BIT0 * SPSR - Serial Peripheral Status Register ($1029) SPIF EQU BIT7 WCOL EQU BIT6 MODF EQU BIT4 *--------------------------------------- * Serial Communications Interface (SCI) * BAUD - Baud Rate Register ($102b) TCLR EQU BIT7 SCP2 EQU BIT6 SCP1 EQU BIT5 SCP0 EQU BIT4 RCKB EQU BIT3 SCR2 EQU BIT2 SCR1 EQU BIT1 SCR0 EQU BIT0 * SCCR1 - Serial Communications Control Register 1 ($102b) R8 EQU BIT7 T8 EQU BIT6 M EQU BIT4 WAKE EQU BIT3 * SCCR2 - Serial Communications Control Register 2 ($102c) ADDR B1 B2 B3 B4 F:\chicken\keyint.asm PAGE 7 TIE EQU BIT7 TCIE EQU BIT6 RIE EQU BIT5 ILIE EQU BIT4 TE EQU BIT3 RE EQU BIT2 RWU EQU BIT1 SBK EQU BIT0 * SCSR - Serial Communications Status Register ($102e) TDRE EQU BIT7 TC EQU BIT6 RDRF EQU BIT5 IDLE EQU BIT4 OR EQU BIT3 NF EQU BIT2 FE EQU BIT1 * SCDR - Serial Communications Data Register ($102f) R7T7 EQU BIT7 R6T6 EQU BIT6 R5T5 EQU BIT5 R4T4 EQU BIT4 R3T3 EQU BIT3 R2T2 EQU BIT2 R1T1 EQU BIT1 R0T0 EQU BIT0 *----------------------------------- * Analog-to-Digital (A2D) Converter * ADCTL - Analog-to-Digital Control Status Register ($1030) CCF EQU BIT7 SCAN EQU BIT5 MULT EQU BIT4 CD EQU BIT3 CC EQU BIT2 CB EQU BIT1 CA EQU BIT0 * BPROT - Block Protect Register ($1035) PTCON EQU BIT4 BPRT3 EQU BIT3 BPRT2 EQU BIT2 BPRT1 EQU BIT1 BRPT0 EQU BIT0 * EPROG - EPROM Programming Control Register ($1036) MBE EQU BIT7 ELAT EQU BIT6 EXCOL EQU BIT5 EXROW EQU BIT4 T1 EQU BIT2 T0 EQU BIT1 PGM EQU BIT0 * OPTION - System Configuration Options Register ($1039) ADPU EQU BIT7 ADDR B1 B2 B3 B4 F:\chicken\keyint.asm PAGE 8 CSEL EQU BIT6 IRQE EQU BIT5 DLY EQU BIT4 CME EQU BIT3 CR1 EQU BIT1 CR0 EQU BIT0 * PPROG - EPROM and EEPROM Programming Control Register . ($103b) ODD EQU BIT7 EVEN EQU BIT6 BYTE EQU BIT4 ROW EQU BIT3 ERASE EQU BIT2 EELAT EQU BIT1 EPGM EQU BIT0 * HPRIO - Highest Priority I Bit Interrupt and Miscellaneous . Register ($103c) RBOOT EQU BIT7 SMOD EQU BIT6 MDA EQU BIT5 IRVNE EQU BIT4 PSEL3 EQU BIT3 PSEL2 EQU BIT2 PSEL1 EQU BIT1 PSEL0 EQU BIT0 * INIT - RAM and I/O Mapping Register ($103d) RAM3 EQU BIT7 RAM2 EQU BIT6 RAM1 EQU BIT5 RAM0 EQU BIT4 REG3 EQU BIT3 REG2 EQU BIT2 REG1 EQU BIT1 REG0 EQU BIT0 * CONFIG - System Configuration Register ($103f) NOSEC EQU BIT3 NOCOP EQU BIT2 ROMON EQU BIT1 EEON EQU BIT0 #include "registers.asm" ; Declares control registers. #include "buffalo.asm" ; Declares utility subroutine . jumptable and ISR jumptable JUMPINST_SIZE equ 1+ADDRSIZE ; A jump instruction . is a 1-byte opcode plus an address * Buffalo subroutine jumptable addresses * Each location in the jump table contains an appropriate JMP . instruction. * To use, just JSR to the jump table address that you want to . use. Buffalo_utljmp_base org $ffa0 UPCASE rmb JUMPINST_SIZE ; Convert character to ADDR B1 B2 B3 B4 F:\chicken\keyint.asm PAGE 9 . uppercase WCHEK rmb JUMPINST_SIZE ; Test character for . whitespace DCHEK rmb JUMPINST_SIZE ; Check character for . delimiter INITDEV rmb JUMPINST_SIZE ; Initialize I/O device INPUT rmb JUMPINST_SIZE ; Read I/O device OUTPUT rmb JUMPINST_SIZE ; Write I/O device OUTLHLF rmb JUMPINST_SIZE ; Convert left nibble to . ASCII and output OUTRHLF rmb JUMPINST_SIZE ; Convert right nibble to . ASCII and output OUTA rmb JUMPINST_SIZE ; Output ASCII character OUT1BYT rmb JUMPINST_SIZE ; Convert binary byte to 2 . ASCII characters and output OUT1BSP rmb JUMPINST_SIZE ; Convert binary byte to 2 . ASCII characters and output followed by space OUT2BSP rmb JUMPINST_SIZE ; Convert 2 consecutive . binary bytes to 4 ASCII characters and output followed by . space OUTCRLF rmb JUMPINST_SIZE ; Output ASCII carriage . return followed by line feed OUTSTRG rmb JUMPINST_SIZE ; Output ASCII string until . end of transmission ($04) OUTSTRG0 rmb JUMPINST_SIZE ; Same as OUTSTRG except . leading carriage return and line feed is skipped INCHAR rmb JUMPINST_SIZE ; Input ASCII character and . echo back VECINIT rmb JUMPINST_SIZE ; Initialize RAM interrupt . vector table * Buffalo interrupt vector jumptable addresses * Each location in the jump table contains an appropriate JMP . instruction. * To use, store the address of your ISR at the jumptable . address+1. Buffalo_intjmp_base org $00c4 JSCI rmb JUMPINST_SIZE ; Serial Communications . Interface JSPI rmb JUMPINST_SIZE ; Serial Peripheral Interface JPAIE rmb JUMPINST_SIZE ; Pulse Accumulator input . edge JPAO rmb JUMPINST_SIZE ; Pulse Accumulator overflow JTOF rmb JUMPINST_SIZE ; Timer overflow JTI4C5 rmb JUMPINST_SIZE ; Timer input capture 4 / . output compare 5 JTOC4 rmb JUMPINST_SIZE ; Timer output compare 4 JTOC3 rmb JUMPINST_SIZE ; Timer output compare 3 JTOC2 rmb JUMPINST_SIZE ; Timer output compare 2 JTOC1 rmb JUMPINST_SIZE ; Timer output compare 1 JTIC3 rmb JUMPINST_SIZE ; Timer input capture 3 JTIC2 rmb JUMPINST_SIZE ; Timer input capture 2 JTIC1 rmb JUMPINST_SIZE ; Timer input capture 1 JRTI rmb JUMPINST_SIZE ; Real-time interrupt JIRQ rmb JUMPINST_SIZE ; IRQ pin (maskable) JXIRQ rmb JUMPINST_SIZE ; XIRQ pin (nonmaskable) JSWI rmb JUMPINST_SIZE ; Software Interrupt JILLOP rmb JUMPINST_SIZE ; Illegal opcode trap JCOP rmb JUMPINST_SIZE ; Computer Operating Properly . watchdog failure JCLM rmb JUMPINST_SIZE ; Clock monitor failure #include "buffalo.asm" ; Declares utility subroutine . jumptable and ISR jumptable ADDR B1 B2 B3 B4 F:\chicken\keyint.asm PAGE 10 org $2000 2000 7E 20 98 main: jmp start #include "delay.asm" ; Delay loop; needed by . keypad.asm. #include "keypad.asm" ; Keypad-related routines. 208A 50 4F 52 54 str1: fcc "PORTD=" . 208E 44 3D 2090 04 fcb $04 2091 50 4F 52 54 str2: fcc "PORTE=" . 2095 45 3D 2097 04 fcb $04 2098 BD 20 17 start: jsr init_keypad ; Initialize port D . for keypad output 209B 7F 10 08 clr PORTD ; Clear all port D . output pins 209E BD 20 C7 jsr setup_irq ; Set up our . interrupt service routine for IRQ. 20A1 CE 20 8A mainloop: ldx #str1 20A4 BD FF CA jsr outstrg0 20A7 CE 10 08 ldx #PORTD 20AA BD FF BE jsr out1bsp 20AD CE 20 91 ldx #str2 20B0 BD FF CA jsr outstrg0 20B3 CE 10 0A ldx #PORTE 20B6 BD FF BE jsr out1bsp 20B9 BD FF C4 jsr outcrlf 20BC CE FF FF ldx #$ffff 20BF BD 20 03 jsr dloop 20C2 3E wai ; Wait for interrupt 20C3 7E 20 A1 jmp mainloop * jsr really_stop ; Stop the CPU till . we get an IRQ. 20C6 39 rts ; Return to caller. * Set up our ISR to be triggered on an IRQ interrupt. 20C7 0F setup_irq: sei ; Set I interrupt . mask (disable IRQ interrupts) 20C8 CE 20 FB ldx #myisr ; Get the address of . our ISR 20CB DF EF stx jirq+1 ; Store it at the IRQ . jumptable address 20CD 0E cli ; Clear I interrupt . mask (enable IRQ interrupts) 20CE 39 rts ; Return from IRQ . setup. * Our interrupt service routine. * Echoes the keypad key that was pressed to the SCI. 20CF 49 6E 74 65 str3: fcc "Interrupted by key: " . 20D3 72 72 75 70 . 20D7 74 74 64 20 . 20DB 62 79 20 6B . 20DF 65 79 3A 20 20E3 04 fcb $04 key: rmb 1 20E5 4F 6F 70 73 str4: fcc "Oops, no key pressed." . 20E9 2C 20 6E 6F ADDR B1 B2 B3 B4 F:\chicken\keyint.asm PAGE 11 . 20ED 20 6B 65 79 . 20F1 20 70 72 65 . 20F5 73 73 65 65 . 20F9 2E 20FA 04 fcb $04 20FB CE 20 CF myisr: ldx #str3 20FE BD FF CA jsr outstrg0 2101 BD 20 43 jsr key_scan ; Scan to see what . key was pressed. 2104 4D tsta ; Was any key . pressed? 2105 27 07 beq nokey ; No; false alarm. 2107 BD FF B8 jsr outa 210A BD FF C4 jsr outcrlf 210D 3B rti 210E CE 20 E5 nokey: ldx #str4 2111 BD FF C7 jsr outstrg 2114 BD FF C4 jsr outcrlf 2117 3B rti ; Return from . interrupt. * Enable the STOP instruction to actually halt the CPU . clocks. enable_stop: 2118 36 psha ; Preserve the caller's A . register. 2119 07 tpa ; Get the CCR bits. 211A 84 7F anda #SFLAG^ALL1S ; Clear the S flag to enable . the STOP instruction. 211C 06 tap ; Set the CCR bits. 211D 32 pula ; Restore the caller's A . register. 211E 39 rts ; Return from enable_stop . subroutine. * Really stop the CPU, until interrupts. * Must enable the STOP instruction first. really_stop: 211F BD 21 18 jsr enable_stop ; Enable the STOP instruction 2122 01 nop ; Use this before STOP, to be . safe. (See ref.man. p.581) 2123 CF stop ; Stop the CPU (until . interrupt) 2124 39 rts ; If we get here, return to . caller. Symbol Table STR3 20CF STR4 20E5 ALL1S 00FF CA 0001 CB 0002 MULT 0010 CC 0004 CD 0008 NOCOP 0004 NOKEY 210E TXD 0002 Symbol Table F:\chicken\keyint.asm PAGE 12 MAINLOOP 20A1 INCHAR FFCD EDG1A 0010 EDG1B 0020 BPRT1 0002 BPRT2 0004 BPRT3 0008 STAF 0080 OPTION 1039 STAI 0040 CONFIG 103F PORTCL 1005 FOC1 0080 FOC2 0040 OUTA FFB8 FOC3 0020 PLS 0004 FOC4 0010 BRPT0 0001 FOC5 0008 PAMOD 0020 DELAY 2081 EDG2A 0004 KEY 20E4 EDG2B 0008 CPOL 0008 PEDGE 0010 PAOVF 0020 PAOVI 0020 TIE 0080 EDG3A 0001 EVEN 0040 IDLE 0010 EDG3B 0002 EXROW 0010 FE 0002 RTIF 0040 M 0010 RTII 0040 PCL0 0001 PCL1 0002 I4O5 0004 PCL2 0004 COPRST 103A TI4O5H 101E R6T6 0040 PCL3 0008 KEY_CHECK 2039 PCL4 0010 CR0 0001 PCL5 0020 CR1 0002 PCL6 0040 TI4O5L 101F PCL7 0080 JCLM 00FD PACTL 1026 REG0 0001 PAEN 0040 EDG4A 0040 KEY_SCAN 2043 REG1 0002 EDG4B 0080 INIT 103D REG2 0004 Symbol Table F:\chicken\keyint.asm PAGE 13 REG3 0008 R3T3 0008 GET_KEY 201D TCTL1 1020 DLOOP 2003 TCTL2 1021 SPIE 0080 SPIF 0080 SPE 0040 EGA 0002 ANY_KEY 2034 R0T0 0001 TDRE 0080 OUTLHLF FFB2 SFLAG 0080 TMSK1 1022 ZFLAG 0004 ODD 0080 DLY 0010 TMSK2 1024 RAM0 0010 RAM1 0020 BIT10 0004 RAM2 0040 SCCR1 102C BIT11 0008 UPCASE FFA0 RAM3 0080 SCCR2 102D BIT12 0010 BIT13 0020 IC1F 0004 BIT14 0040 BIT15 0080 IC1I 0004 EEON 0001 OC1D3 0008 OUTRHLF FFB5 OC1D4 0010 PIOC 1002 OC1D5 0020 OC1D6 0040 NO_KEY 207F OC1D7 0080 BAUD 102B ROW1 0004 ROW2 0008 ROW3 0010 ROW4 0020 DCHEK FFA6 OC1D 100D PR0 0001 JTOC1 00DF PR1 0002 OC1F 0080 JTOC2 00DC EXCOL 0020 JTOC3 00D9 JTOC4 00D6 IC2F 0002 OC1I 0080 EPGM 0001 RWU 0002 IC2I 0002 TIC1H 1010 Symbol Table F:\chicken\keyint.asm PAGE 14 OC1M 100C CWOM 0020 PA0 0001 PA1 0002 ADCTL 1030 TIC1L 1011 PA2 0004 PA3 0008 PA4 0010 PA5 0020 JCOP 00FA VECINIT FFD0 OUTCRLF FFC4 PA6 0040 PA7 0080 BUFFALO_INTJMP_BASE00C4 CCF 0080 EPROG 1036 OC2F 0040 IC3F 0001 OC2I 0040 TOC1H 1016 TFLG1 1023 TFLG2 1025 IC3I 0001 TIC2H 1012 MAIN 2000 TOC1L 1017 PTCON 0010 PAIF 0010 PB0 0001 TCIE 0040 PB1 0001 TIC2L 1013 JTIC1 00E8 JUMPINST_SIZE 0003 PB2 0004 JTIC2 00E5 PAII 0010 PB3 0008 JTIC3 00E2 SCP0 0010 PB4 0010 SCP1 0020 PB5 0020 JRTI 00EB SCP2 0040 PB6 0040 PB7 0080 SBK 0001 OC3F 0020 CFORC 100B OC3I 0020 TOC2H 1018 JIRQ 00EE PSEL0 0001 PSEL1 0002 TIC3H 1014 PSEL2 0004 TOC2L 1019 PSEL3 0008 PC0 0001 PC1 0002 TIC3L 1015 PC2 0004 Symbol Table F:\chicken\keyint.asm PAGE 15 PC3 0008 PC4 0010 PC5 0020 PC6 0040 PC7 0080 TOF 0080 NOSEC 0008 R7T7 0080 TOI 0080 CSEL 0040 RIE 0020 OC4F 0010 MBE 0080 OC4I 0010 TOC3H 101A JSPI 00C7 TOC3L 101B KEY_ROW 2066 CFLAG 0001 PD0 0001 ILIE 0010 PD1 0002 START 2098 R4T4 0010 PD2 0004 PD3 0008 SCR0 0001 PD4 0010 OUT1BSP FFBE SCR1 0002 PD5 0020 XFLAG 0040 SCR2 0004 RBASE 1000 COL1 0001 COL2 0002 COL3 0004 COL4 0008 R1T1 0002 DDRA3 0008 RDRF 0020 MODF 0010 OIN 0008 TOC4H 101C HNDS 0010 DDRA7 0080 TOC4L 101D PE0 0001 PE1 0002 PE2 0004 PE3 0008 PE4 0010 PE5 0020 PE6 0040 PE7 0080 SMOD 0040 ROMON 0002 MDA 0020 JTI4C5 00D3 JILLOP 00F7 NF 0004 TCLR 0080 WCHEK FFA3 RTR0 0001 RTR1 0002 Symbol Table F:\chicken\keyint.asm PAGE 16 HPRIO 103C KEY_DONE 2075 SCAN 0020 OUTSTRG0 FFCA REALLY_STOP 211F OL2 0040 IFLAG 0010 OL3 0010 DDRC0 0001 OL4 0004 DDRC1 0002 OL5 0001 DDRC2 0004 SCSR 102E DDRC3 0008 ADPU 0080 DDRC4 0010 SPR0 0001 DDRC5 0020 SPR1 0002 CPHA 0004 DDRC6 0040 DDRC7 0080 DWOM 0020 MYISR 20FB IRVNE 0010 OR 0008 ADR1 1031 ADR2 1032 JPAO 00CD BUFFALO_UTLJMP_BASEFFA0 ADR3 1033 ADR4 1034 JXIRQ 00F1 OM2 0080 OM3 0020 DDRD0 0001 OM4 0008 DDRD1 0002 OM5 0002 DDRD2 0004 DDRD3 0008 ELAT 0040 DDRD4 0010 DDRD5 0020 PORTA 1000 PORTB 1004 PORTC 1003 PORTD 1008 PORTE 100A BIT0 0001 BIT1 0002 BIT2 0004 BIT3 0008 BIT4 0010 JTOF 00D0 JSCI 00C4 PGM 0001 BIT5 0020 BIT6 0040 BIT7 0080 DDRC 1007 BIT8 0001 DDRD 1009 BIT9 0002 Symbol Table F:\chicken\keyint.asm PAGE 17 INIT_KEYPAD 2017 I4O5F 0008 MSTR 0010 I4O5I 0008 WCOL 0040 R8 0080 PPROG 103B HFLAG 0020 OC1M3 0008 TCNTH 100E OC1M4 0010 SCDR 102F OUTSTRG FFC7 RBOOT 0080 OC1M5 0020 ENABLE_STOP 2118 SETUP_IRQ 20C7 OC1M6 0040 VFLAG 0002 OC1M7 0080 TCNTL 100F SPSR 1029 TABLE 2007 BPROT 1035 RCKB 0008 RE 0004 R5T5 0020 ERASE 0004 INPUT FFAC PACNT 1027 OUT2BSP FFC1 R2T2 0004 JPAIE 00CA RES0 1001 OUT1BYT FFBB ROW 0008 RES1 1006 RES2 1037 RES3 1038 RES4 103E IRQE 0020 INVB 0001 T0 0002 T1 0004 SPCR 1028 WAKE 0008 JSWI 00F4 BYTE 0010 T8 0040 OUTPUT FFAF EELAT 0002 CME 0008 TC 0040 TE 0008 INITDEV FFA9 NFLAG 0008 STR1 208A STR2 2091 ADDRSIZE 0002 SPDR 102A