ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\testint. PAGE 1
* testint.asm - Test interrupt function of HC11.
#include "registers.asm" ; Declares the HC11 control
. registers.
rbase EQU $1000 ; Default base
. address of HC11 I/O control registers
*------------------------------------------------------------
. ----------
* Internal HC11 I/O registers defined as addresses starting
. from rbase.
*------------------------------------------------------------
. ----------
* Parallel I/O registers.
PORTA EQU rbase+$00 ; Port A Data Register
res0 EQU rbase+$01 ; Reserved register #0
PIOC EQU rbase+$02 ; Parallel I/O Control
. Register
PORTC EQU rbase+$03 ; Port C Data Register
PORTB EQU rbase+$04 ; Port B Data Register
PORTCL EQU rbase+$05 ; Port C Latched Register
res1 EQU rbase+$06 ; Reserved register #1
DDRC EQU rbase+$07 ; Port C Data Direction
. Register
PORTD EQU rbase+$08 ; Port D Data Register
DDRD EQU rbase+$09 ; Port D Data Direction
. Register
PORTE EQU rbase+$0a ; Port E Data Register
* Timer system registers.
CFORC EQU rbase+$0b ; Timer Compare Force
. Register
OC1M EQU rbase+$0c ; Output Compare 1 Mask
. Register
OC1D EQU rbase+$0d ; Output Compare 1 Data
. Register
TCNTH EQU rbase+$0e ; Timer Counter Register High
. (MSB)
TCNTL EQU rbase+$0f ; Timer Counter Register Low
. (LSB)
TCNT EQU TCNTH ; Timer Counter Register
. (word)
TIC1H EQU rbase+$10 ; Timer Input Capture 1
. Register High (MSB)
TIC1L EQU rbase+$11 ; Timer Input Capture 1
. Register Low (LSB)
TIC1 EQU TIC1H ; Timer Input Capture 1
. Register (word)
TIC2H EQU rbase+$12 ; Timer Input Capture 2
. Register High (MSB)
TIC2L EQU rbase+$13 ; Timer Input Capture 2
. Register Low (LSB)
TIC2 EQU TIC2H ; Timer Input Capture 2
. Register (word)
TIC3H EQU rbase+$14 ; Timer Input Capture 3
. Register High (MSB)
TIC3L EQU rbase+$15 ; Timer Input Capture 3
. Register Low (LSB)
TIC3 EQU TIC3H ; Timer Input Capture 3
. Register (word)
TOC1H EQU rbase+$16 ; Timer Output Compare 1
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\testint. PAGE 2
. Register High (MSB)
TOC1L EQU rbase+$17 ; Timer Output Compare 1
. Register Low (LSB)
TOC1 EQU TOC1H ; Timer Output Compare 1
. Register (word)
TOC2H EQU rbase+$18 ; Timer Output Compare 2
. Register High (MSB)
TOC2L EQU rbase+$19 ; Timer Output Compare 2
. Register Low (LSB)
TOC2 EQU TOC2H ; Timer Output Compare 2
. Register (word)
TOC3H EQU rbase+$1a ; Timer Output Compare 3
. Register High (MSB)
TOC3L EQU rbase+$1b ; Timer Output Compare 3
. Register Low (LSB)
TOC3 EQU TOC3H ; Timer Output Compare 3
. Register (word)
TOC4H EQU rbase+$1c ; Timer Output Compare 4
. Register High (MSB)
TOC4L EQU rbase+$1d ; Timer Output Compare 4
. Register Low (LSB)
TOC4 EQU TOC4H ; Timer Output Compare 4
. Register (word)
TI4O5H EQU rbase+$1e ; Timer Input Capture 4/
. Output Compare 5 Register High (MSB)
TI4O5L EQU rbase+$1f ; Timer Input Capture 4/
. Output Compare 5 Register Low (LSB)
TI4O5 EQU TI4O5H ; Timer Input Capture 4/
. Output Compare 5 Register (word)
TIC4 EQU TI4O5 ; Timer Input Capture 4
. (word)
TOC5 EQU TI4O5 ; Timer Output Compare 5
. (word)
TCTL1 EQU rbase+$20 ; Timer Control Register 1
TCTL2 EQU rbase+$21 ; Timer Control Register 2
TMSK1 EQU rbase+$22 ; Timer Interrupt Mask 1
. Register
TFLG1 EQU rbase+$23 ; Timer Interrupt Flag 1
TMSK2 EQU rbase+$24 ; Timer Interrupt Mask 2
. Register
TFLG2 EQU rbase+$25 ; Timer Interrupt Flag 2
PACTL EQU rbase+$26 ; Pulse Accumulator Control
. Register
PACNT EQU rbase+$27 ; Pulse Accumulator Count
. Register
* Serial Peripheral Interface (SPI) registers.
SPCR EQU rbase+$28 ; Serial Peripheral Control
. Register
SPSR EQU rbase+$29 ; Serial Peripheral Status
. Register
SPDR EQU rbase+$2a ; Serial Peripheral Data I/O
. Register
* Serial Communications Interface (SCI) registers.
BAUD EQU rbase+$2b ; Baud Rate Register
SCCR1 EQU rbase+$2c ; Serial Communications
. Control Register 1
SCCR2 EQU rbase+$2d ; Serial Communications
. Control Register 2
SCSR EQU rbase+$2e ; Serial Communications
. Status Register
SCDR EQU rbase+$2f ; Serial Communications Data
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\testint. PAGE 3
. Register
* Analog-to-Digital (A2D) system registers.
ADCTL EQU rbase+$30 ; Analog-to-Digital Control
. Status Register
ADR1 EQU rbase+$31 ; Analog-to-Digital Results
. Register 1
ADR2 EQU rbase+$32 ; Analog-to-Digital Results
. Register 2
ADR3 EQU rbase+$33 ; Analog-to-Digital Results
. Register 3
ADR4 EQU rbase+$34 ; Analog-to-Digital Results
. Register 4
* Miscellaneous control and configuration registers.
BPROT EQU rbase+$35 ; Block Protect Register
EPROG EQU rbase+$36 ; EPROM Programming Control
. Register (711E20 only)
res2 EQU rbase+$37 ; Reserved register #2
res3 EQU rbase+$38 ; Reserved register #3
OPTION EQU rbase+$39 ; System Configuration
. Options Register
COPRST EQU rbase+$3a ; Arm/Reset COP Timer
. Circuitry Register
PPROG EQU rbase+$3b ; EPROM and EEPROM
. Programming Control Register
HPRIO EQU rbase+$3c ; Highest Priority I Bit
. Interrupt and Miscellaneous Reigster
INIT EQU rbase+$3d ; RAM and I/O Mapping
. Register
res4 EQU rbase+$3e ; Reserved register #4
CONFIG EQU rbase+$3f ; System Configuration
. Register
*----------------------------------------------------------
* Individual register bits.
* See datasheet for full descriptions. (Index on pp.38-43.)
*
* To use these, use BSET, BCLR, BRSET, BRCLR instructions
* on the appropriate register address and with an
* appropriate mask (logical OR of bits that you want).
*----------------------------------------------------------
*----------------
* Parallel Ports
* PORTA - Port A Data Register ($1000)
PA7 EQU BIT7
PA6 EQU BIT6
PA5 EQU BIT5
PA4 EQU BIT4
PA3 EQU BIT3
PA2 EQU BIT2
PA1 EQU BIT1
PA0 EQU BIT0
* PIOC - Parallel I/O Control Register ($1002)
STAF EQU BIT7
STAI EQU BIT6
CWOM EQU BIT5
HNDS EQU BIT4
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\testint. PAGE 4
OIN EQU BIT3
PLS EQU BIT2
EGA EQU BIT1
INVB EQU BIT0
* PORTC - Port C Data Register ($1003)
PC7 EQU BIT7
PC6 EQU BIT6
PC5 EQU BIT5
PC4 EQU BIT4
PC3 EQU BIT3
PC2 EQU BIT2
PC1 EQU BIT1
PC0 EQU BIT0
* PORTB - Port B Data Register ($1004)
PB7 EQU BIT7
PB6 EQU BIT6
PB5 EQU BIT5
PB4 EQU BIT4
PB3 EQU BIT3
PB2 EQU BIT2
PB1 EQU BIT1
PB0 EQU BIT0
* PORTCL - Port C Latched Register ($1005)
PCL7 EQU BIT7
PCL6 EQU BIT6
PCL5 EQU BIT5
PCL4 EQU BIT4
PCL3 EQU BIT3
PCL2 EQU BIT2
PCL1 EQU BIT1
PCL0 EQU BIT0
* DDRC - Port C Data Direction Register ($1007)
DDRC7 EQU BIT7
DDRC6 EQU BIT6
DDRC5 EQU BIT5
DDRC4 EQU BIT4
DDRC3 EQU BIT3
DDRC2 EQU BIT2
DDRC1 EQU BIT1
DDRC0 EQU BIT0
* PORTD - Port D Data Register ($1008)
PD5 EQU BIT5
PD4 EQU BIT4
PD3 EQU BIT3
PD2 EQU BIT2
PD1 EQU BIT1
PD0 EQU BIT0
* DDRD - Port D Data Register ($1009)
DDRD5 EQU BIT5
DDRD4 EQU BIT4
DDRD3 EQU BIT3
DDRD2 EQU BIT2
DDRD1 EQU BIT1
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\testint. PAGE 5
DDRD0 EQU BIT0
* PORTE - Port E Data Register ($100a)
PE7 EQU BIT7
PE6 EQU BIT6
PE5 EQU BIT5
PE4 EQU BIT4
PE3 EQU BIT3
PE2 EQU BIT2
PE1 EQU BIT1
PE0 EQU BIT0
*-----------------
* Timer facility
* CFORC - Timer Compare Force Register ($100b)
FOC1 EQU BIT7
FOC2 EQU BIT6
FOC3 EQU BIT5
FOC4 EQU BIT4
FOC5 EQU BIT3
* OC1M - Output Compare 1 Mask Register ($100c)
OC1M7 EQU BIT7
OC1M6 EQU BIT6
OC1M5 EQU BIT5
OC1M4 EQU BIT4
OC1M3 EQU BIT3
* OC1D - Output Compare 1 Data Register ($100d)
OC1D7 EQU BIT7
OC1D6 EQU BIT6
OC1D5 EQU BIT5
OC1D4 EQU BIT4
OC1D3 EQU BIT3
* TCTL1 - Timer Control Register 1 ($1020)
OM2 EQU BIT7
OL2 EQU BIT6
OM3 EQU BIT5
OL3 EQU BIT4
OM4 EQU BIT3
OL4 EQU BIT2
OM5 EQU BIT1
OL5 EQU BIT0
* TCTL2 - Timer Control Register 2 ($1021)
EDG4B EQU BIT7
EDG4A EQU BIT6
EDG1B EQU BIT5
EDG1A EQU BIT4
EDG2B EQU BIT3
EDG2A EQU BIT2
EDG3B EQU BIT1
EDG3A EQU BIT0
* TMSK1 - Timer Interrupt Mask 1 Register ($1022)
OC1I EQU BIT7
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\testint. PAGE 6
OC2I EQU BIT6
OC3I EQU BIT5
OC4I EQU BIT4
I4O5I EQU BIT3
OC5I EQU I4O5I
IC4I EQU I4O5I
IC1I EQU BIT2
IC2I EQU BIT1
IC3I EQU BIT0
* TFLG1 - Timer Interrupt Flag 1 ($1023)
OC1F EQU BIT7
OC2F EQU BIT6
OC3F EQU BIT5
OC4F EQU BIT4
I4O5F EQU BIT3
OC5F EQU I4O5F
IC4F EQU I4O5F
IC1F EQU BIT2
IC2F EQU BIT1
IC3F EQU BIT0
* TMSK2 - Timer Interrupt Mask 2 Register ($1024)
TOI EQU BIT7
RTII EQU BIT6
PAOVI EQU BIT5
PAII EQU BIT4
PR1 EQU BIT1
PR0 EQU BIT0
* TFLG2 - Timer Interrupt Flag 2 ($1025)
TOF EQU BIT7
RTIF EQU BIT6
PAOVF EQU BIT5
PAIF EQU BIT4
* PACTL - Pulse Accumulator Control Register ($1026)
DDRA7 EQU BIT7
PAEN EQU BIT6
PAMOD EQU BIT5
PEDGE EQU BIT4
DDRA3 EQU BIT3
I4O5 EQU BIT2
RTR1 EQU BIT1
RTR0 EQU BIT0
*-----------------------------------
* Serial Peripheral Interface (SPI)
* SPCR - Serial Peripheral Control Register ($1028)
SPIE EQU BIT7
SPE EQU BIT6
DWOM EQU BIT5
MSTR EQU BIT4
CPOL EQU BIT3
CPHA EQU BIT2
SPR1 EQU BIT1
SPR0 EQU BIT0
* SPSR - Serial Peripheral Status Register ($1029)
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\testint. PAGE 7
SPIF EQU BIT7
WCOL EQU BIT6
MODF EQU BIT4
*---------------------------------------
* Serial Communications Interface (SCI)
* BAUD - Baud Rate Register ($102b)
TCLR EQU BIT7
SCP2 EQU BIT6
SCP1 EQU BIT5
SCP0 EQU BIT4
RCKB EQU BIT3
SCR2 EQU BIT2
SCR1 EQU BIT1
SCR0 EQU BIT0
* SCCR1 - Serial Communications Control Register 1 ($102b)
R8 EQU BIT7
T8 EQU BIT6
M EQU BIT4
WAKE EQU BIT3
* SCCR2 - Serial Communications Control Register 2 ($102c)
TIE EQU BIT7
TCIE EQU BIT6
RIE EQU BIT5
ILIE EQU BIT4
TE EQU BIT3
RE EQU BIT2
RWU EQU BIT1
SBK EQU BIT0
* SCSR - Serial Communications Status Register ($102e)
TDRE EQU BIT7
TC EQU BIT6
RDRF EQU BIT5
IDLE EQU BIT4
OR EQU BIT3
NF EQU BIT2
FE EQU BIT1
* SCDR - Serial Communications Data Register ($102f)
R7T7 EQU BIT7
R6T6 EQU BIT6
R5T5 EQU BIT5
R4T4 EQU BIT4
R3T3 EQU BIT3
R2T2 EQU BIT2
R1T1 EQU BIT1
R0T0 EQU BIT0
*-----------------------------------
* Analog-to-Digital (A2D) Converter
* ADCTL - Analog-to-Digital Control Status Register ($1030)
CCF EQU BIT7
SCAN EQU BIT5
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\testint. PAGE 8
MULT EQU BIT4
CD EQU BIT3
CC EQU BIT2
CB EQU BIT1
CA EQU BIT0
* BPROT - Block Protect Register ($1035)
PTCON EQU BIT4
BPRT3 EQU BIT3
BPRT2 EQU BIT2
BPRT1 EQU BIT1
BRPT0 EQU BIT0
* EPROG - EPROM Programming Control Register ($1036)
MBE EQU BIT7
ELAT EQU BIT6
EXCOL EQU BIT5
EXROW EQU BIT4
T1 EQU BIT2
T0 EQU BIT1
PGM EQU BIT0
* OPTION - System Configuration Options Register ($1039)
ADPU EQU BIT7
CSEL EQU BIT6
IRQE EQU BIT5
DLY EQU BIT4
CME EQU BIT3
CR1 EQU BIT1
CR0 EQU BIT0
* PPROG - EPROM and EEPROM Programming Control Register
. ($103b)
ODD EQU BIT7
EVEN EQU BIT6
BYTE EQU BIT4
ROW EQU BIT3
ERASE EQU BIT2
EELAT EQU BIT1
EPGM EQU BIT0
* HPRIO - Highest Priority I Bit Interrupt and Miscellaneous
. Register ($103c)
RBOOT EQU BIT7
SMOD EQU BIT6
MDA EQU BIT5
IRVNE EQU BIT4
PSEL3 EQU BIT3
PSEL2 EQU BIT2
PSEL1 EQU BIT1
PSEL0 EQU BIT0
* INIT - RAM and I/O Mapping Register ($103d)
RAM3 EQU BIT7
RAM2 EQU BIT6
RAM1 EQU BIT5
RAM0 EQU BIT4
REG3 EQU BIT3
REG2 EQU BIT2
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\testint. PAGE 9
REG1 EQU BIT1
REG0 EQU BIT0
* CONFIG - System Configuration Register ($103f)
NOSEC EQU BIT3
NOCOP EQU BIT2
ROMON EQU BIT1
EEON EQU BIT0
#include "registers.asm" ; Declares the HC11 control
. registers.
#include "vectors.asm" ; Declares interrupt & reset
. vectors.
VECSIZE equ ADDRSIZE ; A vector is just an
. address
Vbase_spec equ $bfc0 ; Base of vector region in
. special modes.
* Vector addresses in normal MCU modes. For special modes,
. subtract (vbase-vbase_spec).
Vbase org $ffd6 ; Base of vector region in normal
. modes
VSCI rmb VECSIZE ; Serial Communications Interface
VSPI rmb VECSIZE ; Serial Peripheral Interface
VPAIE rmb VECSIZE ; Pulse Accumulator input edge
VPAO rmb VECSIZE ; Pulse Accumulator overflow
VTOF rmb VECSIZE ; Timer overflow
VTI4C5 rmb VECSIZE ; Timer input capture 4 / output
. compare 5
VTOC4 rmb VECSIZE ; Timer output compare 4
VTOC3 rmb VECSIZE ; Timer output compare 3
VTOC2 rmb VECSIZE ; Timer output compare 2
VTOC1 rmb VECSIZE ; Timer output compare 1
VTIC3 rmb VECSIZE ; Timer input capture 3
VTIC2 rmb VECSIZE ; Timer input capture 2
VTIC1 rmb VECSIZE ; Timer input capture 1
VRTI rmb VECSIZE ; Real-time interrupt
VIRQ rmb VECSIZE ; IRQ pin (maskable)
VXIRQ rmb VECSIZE ; XIRQ pin (nonmaskable)
VSWI rmb VECSIZE ; Software Interrupt
VILLOP rmb VECSIZE ; Illegal opcode trap
VCOP rmb VECSIZE ; Computer Operating Properly
. watchdog failure
VCLM rmb VECSIZE ; Clock monitor failure
VRST rmb VECSIZE ; RESET pin vector
#include "vectors.asm" ; Declares interrupt & reset
. vectors.
org $2000
main:
* Set IRQ for falling-edge-detect mode.
* This must be done in the 1st 64 cycles out of reset.
2000 CE 10 39 ldx #OPTION ; Point X at the OPTION
. register
2003 1C 00 20 bset 0,X IRQE ; Set the IRQE bit in the
. OPTION register
* Turn on bits DDRD0-DDRD5 in data direction register D to
. make PD0-PD5 outputs.
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\testint. PAGE 10
2006 CE 10 09 ldx #DDRD
2009 1C 00 3F bset 0,X DDRD5|DDRD4|DDRD3|DDRD2|DDRD1|DDRD0
200C 0E cli ; Clear I interrupt mask (enable IRQ
. interrupts)
200D 7C 10 08 loop1: inc PORTD ; Increment port D contents.
2010 20 FB bra loop1 ; Just keep doing this forever.
2012 7C 10 04 myISR: inc PORTB ; Increment port B contents.
2015 26 FB bne myISR ; Keep going till it gets back to 0.
2017 3B rti ; Return from interrupt.
*----------------------------------------------------
* EEPROM region
* Establish our interrupt and reset vectors in ROM.
*----------------------------------------------------
org VIRQ ; Point the IRQ interrupt vector...
FFF2 20 12 fdb myISR ; ...at my Interrupt Service Routine.
org VRST ; Point the RESET vector...
FFFE 20 00 fdb main ; ...at my main routine.
Symbol Table
ALL1S 00FF
VBASE FFD6
CA 0001
CB 0002
MULT 0010
CC 0004
CD 0008
NOCOP 0004
VSWI FFF6
VXIRQ FFF4
EDG1A 0010
EDG1B 0020
BPRT1 0002
BPRT2 0004
BPRT3 0008
STAF 0080
OPTION 1039
STAI 0040
CONFIG 103F
PORTCL 1005
FOC1 0080
FOC2 0040
FOC3 0020
PLS 0004
FOC4 0010
BRPT0 0001
FOC5 0008
LOOP1 200D
PAMOD 0020
EDG2A 0004
EDG2B 0008
CPOL 0008
PEDGE 0010
VECSIZE 0002
PAOVF 0020
PAOVI 0020
TIE 0080
EDG3A 0001
Symbol Table X:\public_html\EEL4746\programs\library\testint. PAGE 11
EVEN 0040
IDLE 0010
EDG3B 0002
EXROW 0010
FE 0002
RTIF 0040
M 0010
RTII 0040
PCL0 0001
PCL1 0002
I4O5 0004
PCL2 0004
COPRST 103A
TI4O5H 101E
R6T6 0040
PCL3 0008
PCL4 0010
CR0 0001
PCL5 0020
CR1 0002
PCL6 0040
TI4O5L 101F
VPAIE FFDA
PCL7 0080
PACTL 1026
REG0 0001
PAEN 0040
EDG4A 0040
REG1 0002
EDG4B 0080
INIT 103D
REG2 0004
REG3 0008
R3T3 0008
TCTL1 1020
TCTL2 1021
SPIE 0080
SPIF 0080
SPE 0040
EGA 0002
TI4O5 101E
R0T0 0001
TDRE 0080
SFLAG 0080
TMSK1 1022
ZFLAG 0004
JUMPSIZE 0003
ODD 0080
DLY 0010
TMSK2 1024
RAM0 0010
RAM1 0020
BIT10 0004
RAM2 0040
SCCR1 102C
BIT11 0008
RAM3 0080
SCCR2 102D
BIT12 0010
BIT13 0020
IC1F 0004
BIT14 0040
BIT15 0080
VCLM FFFC
IC1I 0004
Symbol Table X:\public_html\EEL4746\programs\library\testint. PAGE 12
EEON 0001
OC1D3 0008
OC1D4 0010
PIOC 1002
OC1D5 0020
OC1D6 0040
OC1D7 0080
BAUD 102B
OC1D 100D
PR0 0001
PR1 0002
OC1F 0080
EXCOL 0020
IC2F 0002
OC1I 0080
EPGM 0001
RWU 0002
IC2I 0002
TIC1H 1010
OC1M 100C
CWOM 0020
PA0 0001
PA1 0002
ADCTL 1030
TIC1L 1011
PA2 0004
PA3 0008
PA4 0010
PA5 0020
PA6 0040
PA7 0080
CCF 0080
EPROG 1036
VTI4C5 FFE0
VILLOP FFF8
OC2F 0040
IC3F 0001
OC2I 0040
TOC1H 1016
TFLG1 1023
TFLG2 1025
IC3I 0001
TIC2H 1012
MAIN 2000
TOC1L 1017
PTCON 0010
PAIF 0010
PB0 0001
TCIE 0040
PB1 0002
TIC2L 1013
PB2 0004
PAII 0010
PB3 0008
SCP0 0010
PB4 0010
SCP1 0020
PB5 0020
SCP2 0040
PB6 0040
PB7 0080
SBK 0001
OC3F 0020
CFORC 100B
IC4F 0008
Symbol Table X:\public_html\EEL4746\programs\library\testint. PAGE 13
OC3I 0020
TOC2H 1018
PSEL0 0001
PSEL1 0002
IC4I 0008
TIC3H 1014
PSEL2 0004
TOC2L 1019
PSEL3 0008
VCOP FFFA
PC0 0001
PC1 0002
TIC3L 1015
PC2 0004
PC3 0008
PC4 0010
PC5 0020
PC6 0040
PC7 0080
TOF 0080
NOSEC 0008
VRST FFFE
R7T7 0080
TOI 0080
CSEL 0040
RIE 0020
OC4F 0010
MBE 0080
OC4I 0010
TOC3H 101A
TOC3L 101B
VRTI FFF0
CFLAG 0001
PD0 0001
ILIE 0010
PD1 0002
R4T4 0010
PD2 0004
PD3 0008
SCR0 0001
PD4 0010
SCR1 0002
PD5 0020
XFLAG 0040
SCR2 0004
RBASE 1000
VIRQ FFF2
OC5F 0008
R1T1 0002
DDRA3 0008
RDRF 0020
MODF 0010
OC5I 0008
OIN 0008
TOC4H 101C
HNDS 0010
DDRA7 0080
TOC4L 101D
PE0 0001
PE1 0002
PE2 0004
PE3 0008
PE4 0010
PE5 0020
PE6 0040
Symbol Table X:\public_html\EEL4746\programs\library\testint. PAGE 14
PE7 0080
SMOD 0040
ROMON 0002
MDA 0020
VSPI FFD8
NF 0004
TCLR 0080
RTR0 0001
WORDSIZE 0002
RTR1 0002
VTOC1 FFE8
HPRIO 103C
VTOC2 FFE6
VTOC3 FFE4
VTOC4 FFE2
SCAN 0020
OL2 0040
IFLAG 0010
OL3 0010
DDRC0 0001
OL4 0004
DDRC1 0002
OL5 0001
DDRC2 0004
SCSR 102E
DDRC3 0008
ADPU 0080
DDRC4 0010
SPR0 0001
DDRC5 0020
SPR1 0002
CPHA 0004
DDRC6 0040
DDRC7 0080
DWOM 0020
MYISR 2012
IRVNE 0010
OR 0008
ADR1 1031
VTIC1 FFEE
ADR2 1032
VTIC2 FFEC
ADR3 1033
VTIC3 FFEA
ADR4 1034
OM2 0080
OM3 0020
DDRD0 0001
OM4 0008
DDRD1 0002
OM5 0002
DDRD2 0004
DDRD3 0008
TCNT 100E
ELAT 0040
DDRD4 0010
DDRD5 0020
PORTA 1000
PORTB 1004
PORTC 1003
PORTD 1008
PORTE 100A
BIT0 0001
BIT1 0002
BIT2 0004
Symbol Table X:\public_html\EEL4746\programs\library\testint. PAGE 15
BIT3 0008
BIT4 0010
PGM 0001
BIT5 0020
BIT6 0040
BIT7 0080
DDRC 1007
BIT8 0001
DDRD 1009
BIT9 0002
I4O5F 0008
MSTR 0010
I4O5I 0008
WCOL 0040
VPAO FFDC
R8 0080
PPROG 103B
HFLAG 0020
OC1M3 0008
TCNTH 100E
OC1M4 0010
SCDR 102F
RBOOT 0080
OC1M5 0020
OC1M6 0040
VFLAG 0002
OC1M7 0080
TCNTL 100F
SPSR 1029
BPROT 1035
RCKB 0008
RE 0004
TOC1 1016
R5T5 0020
TOC2 1018
TOC3 101A
ERASE 0004
TOC4 101C
TOC5 101E
VTOF FFDE
VSCI FFD6
PACNT 1027
R2T2 0004
RES0 1001
ROW 0008
RES1 1006
RES2 1037
RES3 1038
RES4 103E
IRQE 0020
INVB 0001
T0 0002
T1 0004
SPCR 1028
WAKE 0008
BYTE 0010
T8 0040
EELAT 0002
TIC1 1010
TIC2 1012
TIC3 1014
TIC4 101E
VBASE_SPEC BFC0
CME 0008
TC 0040
Symbol Table X:\public_html\EEL4746\programs\library\testint. PAGE 16
TE 0008
NFLAG 0008
ADDRSIZE 0002
SPDR 102A