ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 1
* timertest.asm
* Test our ability to move characters around the display at
. will
* under control of the HC11 timer.
#include "ascii.asm"
#include "registers.asm"
rbase EQU $1000 ; Default base
. address of HC11 I/O control registers
*------------------------------------------------------------
. ----------
* Internal HC11 I/O registers defined as addresses starting
. from rbase.
*------------------------------------------------------------
. ----------
* Parallel I/O registers.
PORTA EQU rbase+$00 ; Port A Data Register
res0 EQU rbase+$01 ; Reserved register #0
PIOC EQU rbase+$02 ; Parallel I/O Control
. Register
PORTC EQU rbase+$03 ; Port C Data Register
PORTB EQU rbase+$04 ; Port B Data Register
PORTCL EQU rbase+$05 ; Port C Latched Register
res1 EQU rbase+$06 ; Reserved register #1
DDRC EQU rbase+$07 ; Port C Data Direction
. Register
PORTD EQU rbase+$08 ; Port D Data Register
DDRD EQU rbase+$09 ; Port D Data Direction
. Register
PORTE EQU rbase+$0a ; Port E Data Register
* Timer system registers.
CFORC EQU rbase+$0b ; Timer Compare Force
. Register
OC1M EQU rbase+$0c ; Output Compare 1 Mask
. Register
OC1D EQU rbase+$0d ; Output Compare 1 Data
. Register
TCNTH EQU rbase+$0e ; Timer Counter Register High
. (MSB)
TCNTL EQU rbase+$0f ; Timer Counter Register Low
. (LSB)
TCNT EQU TCNTH ; Timer Counter Register
. (word)
TIC1H EQU rbase+$10 ; Timer Input Capture 1
. Register High (MSB)
TIC1L EQU rbase+$11 ; Timer Input Capture 1
. Register Low (LSB)
TIC1 EQU TIC1H ; Timer Input Capture 1
. Register (word)
TIC2H EQU rbase+$12 ; Timer Input Capture 2
. Register High (MSB)
TIC2L EQU rbase+$13 ; Timer Input Capture 2
. Register Low (LSB)
TIC2 EQU TIC2H ; Timer Input Capture 2
. Register (word)
TIC3H EQU rbase+$14 ; Timer Input Capture 3
. Register High (MSB)
TIC3L EQU rbase+$15 ; Timer Input Capture 3
. Register Low (LSB)
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 2
TIC3 EQU TIC3H ; Timer Input Capture 3
. Register (word)
TOC1H EQU rbase+$16 ; Timer Output Compare 1
. Register High (MSB)
TOC1L EQU rbase+$17 ; Timer Output Compare 1
. Register Low (LSB)
TOC1 EQU TOC1H ; Timer Output Compare 1
. Register (word)
TOC2H EQU rbase+$18 ; Timer Output Compare 2
. Register High (MSB)
TOC2L EQU rbase+$19 ; Timer Output Compare 2
. Register Low (LSB)
TOC2 EQU TOC2H ; Timer Output Compare 2
. Register (word)
TOC3H EQU rbase+$1a ; Timer Output Compare 3
. Register High (MSB)
TOC3L EQU rbase+$1b ; Timer Output Compare 3
. Register Low (LSB)
TOC3 EQU TOC3H ; Timer Output Compare 3
. Register (word)
TOC4H EQU rbase+$1c ; Timer Output Compare 4
. Register High (MSB)
TOC4L EQU rbase+$1d ; Timer Output Compare 4
. Register Low (LSB)
TOC4 EQU TOC4H ; Timer Output Compare 4
. Register (word)
TI4O5H EQU rbase+$1e ; Timer Input Capture 4/
. Output Compare 5 Register High (MSB)
TI4O5L EQU rbase+$1f ; Timer Input Capture 4/
. Output Compare 5 Register Low (LSB)
TI4O5 EQU TI4O5H ; Timer Input Capture 4/
. Output Compare 5 Register (word)
TIC4 EQU TI4O5 ; Timer Input Capture 4
. (word)
TOC5 EQU TI4O5 ; Timer Output Compare 5
. (word)
TCTL1 EQU rbase+$20 ; Timer Control Register 1
TCTL2 EQU rbase+$21 ; Timer Control Register 2
TMSK1 EQU rbase+$22 ; Timer Interrupt Mask 1
. Register
TFLG1 EQU rbase+$23 ; Timer Interrupt Flag 1
TMSK2 EQU rbase+$24 ; Timer Interrupt Mask 2
. Register
TFLG2 EQU rbase+$25 ; Timer Interrupt Flag 2
PACTL EQU rbase+$26 ; Pulse Accumulator Control
. Register
PACNT EQU rbase+$27 ; Pulse Accumulator Count
. Register
* Serial Peripheral Interface (SPI) registers.
SPCR EQU rbase+$28 ; Serial Peripheral Control
. Register
SPSR EQU rbase+$29 ; Serial Peripheral Status
. Register
SPDR EQU rbase+$2a ; Serial Peripheral Data I/O
. Register
* Serial Communications Interface (SCI) registers.
BAUD EQU rbase+$2b ; Baud Rate Register
SCCR1 EQU rbase+$2c ; Serial Communications
. Control Register 1
SCCR2 EQU rbase+$2d ; Serial Communications
. Control Register 2
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 3
SCSR EQU rbase+$2e ; Serial Communications
. Status Register
SCDR EQU rbase+$2f ; Serial Communications Data
. Register
* Analog-to-Digital (A2D) system registers.
ADCTL EQU rbase+$30 ; Analog-to-Digital Control
. Status Register
ADR1 EQU rbase+$31 ; Analog-to-Digital Results
. Register 1
ADR2 EQU rbase+$32 ; Analog-to-Digital Results
. Register 2
ADR3 EQU rbase+$33 ; Analog-to-Digital Results
. Register 3
ADR4 EQU rbase+$34 ; Analog-to-Digital Results
. Register 4
* Miscellaneous control and configuration registers.
BPROT EQU rbase+$35 ; Block Protect Register
EPROG EQU rbase+$36 ; EPROM Programming Control
. Register (711E20 only)
res2 EQU rbase+$37 ; Reserved register #2
res3 EQU rbase+$38 ; Reserved register #3
OPTION EQU rbase+$39 ; System Configuration
. Options Register
COPRST EQU rbase+$3a ; Arm/Reset COP Timer
. Circuitry Register
PPROG EQU rbase+$3b ; EPROM and EEPROM
. Programming Control Register
HPRIO EQU rbase+$3c ; Highest Priority I Bit
. Interrupt and Miscellaneous Reigster
INIT EQU rbase+$3d ; RAM and I/O Mapping
. Register
res4 EQU rbase+$3e ; Reserved register #4
CONFIG EQU rbase+$3f ; System Configuration
. Register
*----------------------------------------------------------
* Individual register bits.
* See datasheet for full descriptions. (Index on pp.38-43.)
*
* To use these, use BSET, BCLR, BRSET, BRCLR instructions
* on the appropriate register address and with an
* appropriate mask (logical OR of bits that you want).
*----------------------------------------------------------
*----------------
* Parallel Ports
* PORTA - Port A Data Register ($1000)
PA7 EQU BIT7
PA6 EQU BIT6
PA5 EQU BIT5
PA4 EQU BIT4
PA3 EQU BIT3
PA2 EQU BIT2
PA1 EQU BIT1
PA0 EQU BIT0
* PIOC - Parallel I/O Control Register ($1002)
STAF EQU BIT7
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 4
STAI EQU BIT6
CWOM EQU BIT5
HNDS EQU BIT4
OIN EQU BIT3
PLS EQU BIT2
EGA EQU BIT1
INVB EQU BIT0
* PORTC - Port C Data Register ($1003)
PC7 EQU BIT7
PC6 EQU BIT6
PC5 EQU BIT5
PC4 EQU BIT4
PC3 EQU BIT3
PC2 EQU BIT2
PC1 EQU BIT1
PC0 EQU BIT0
* PORTB - Port B Data Register ($1004)
PB7 EQU BIT7
PB6 EQU BIT6
PB5 EQU BIT5
PB4 EQU BIT4
PB3 EQU BIT3
PB2 EQU BIT2
PB1 EQU BIT1
PB0 EQU BIT0
* PORTCL - Port C Latched Register ($1005)
PCL7 EQU BIT7
PCL6 EQU BIT6
PCL5 EQU BIT5
PCL4 EQU BIT4
PCL3 EQU BIT3
PCL2 EQU BIT2
PCL1 EQU BIT1
PCL0 EQU BIT0
* DDRC - Port C Data Direction Register ($1007)
DDRC7 EQU BIT7
DDRC6 EQU BIT6
DDRC5 EQU BIT5
DDRC4 EQU BIT4
DDRC3 EQU BIT3
DDRC2 EQU BIT2
DDRC1 EQU BIT1
DDRC0 EQU BIT0
* PORTD - Port D Data Register ($1008)
PD5 EQU BIT5
PD4 EQU BIT4
PD3 EQU BIT3
PD2 EQU BIT2
PD1 EQU BIT1
PD0 EQU BIT0
* DDRD - Port D Data Register ($1009)
DDRD5 EQU BIT5
DDRD4 EQU BIT4
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 5
DDRD3 EQU BIT3
DDRD2 EQU BIT2
DDRD1 EQU BIT1
DDRD0 EQU BIT0
* PORTE - Port E Data Register ($100a)
PE7 EQU BIT7
PE6 EQU BIT6
PE5 EQU BIT5
PE4 EQU BIT4
PE3 EQU BIT3
PE2 EQU BIT2
PE1 EQU BIT1
PE0 EQU BIT0
*-----------------
* Timer facility
* CFORC - Timer Compare Force Register ($100b)
FOC1 EQU BIT7
FOC2 EQU BIT6
FOC3 EQU BIT5
FOC4 EQU BIT4
FOC5 EQU BIT3
* OC1M - Output Compare 1 Mask Register ($100c)
OC1M7 EQU BIT7
OC1M6 EQU BIT6
OC1M5 EQU BIT5
OC1M4 EQU BIT4
OC1M3 EQU BIT3
* OC1D - Output Compare 1 Data Register ($100d)
OC1D7 EQU BIT7
OC1D6 EQU BIT6
OC1D5 EQU BIT5
OC1D4 EQU BIT4
OC1D3 EQU BIT3
* TCTL1 - Timer Control Register 1 ($1020)
OM2 EQU BIT7
OL2 EQU BIT6
OM3 EQU BIT5
OL3 EQU BIT4
OM4 EQU BIT3
OL4 EQU BIT2
OM5 EQU BIT1
OL5 EQU BIT0
* TCTL2 - Timer Control Register 2 ($1021)
EDG4B EQU BIT7
EDG4A EQU BIT6
EDG1B EQU BIT5
EDG1A EQU BIT4
EDG2B EQU BIT3
EDG2A EQU BIT2
EDG3B EQU BIT1
EDG3A EQU BIT0
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 6
* TMSK1 - Timer Interrupt Mask 1 Register ($1022)
OC1I EQU BIT7
OC2I EQU BIT6
OC3I EQU BIT5
OC4I EQU BIT4
I4O5I EQU BIT3
OC5I EQU I4O5I
IC4I EQU I4O5I
IC1I EQU BIT2
IC2I EQU BIT1
IC3I EQU BIT0
* TFLG1 - Timer Interrupt Flag 1 ($1023)
OC1F EQU BIT7
OC2F EQU BIT6
OC3F EQU BIT5
OC4F EQU BIT4
I4O5F EQU BIT3
OC5F EQU I4O5F
IC4F EQU I4O5F
IC1F EQU BIT2
IC2F EQU BIT1
IC3F EQU BIT0
* TMSK2 - Timer Interrupt Mask 2 Register ($1024)
TOI EQU BIT7
RTII EQU BIT6
PAOVI EQU BIT5
PAII EQU BIT4
PR1 EQU BIT1
PR0 EQU BIT0
* TFLG2 - Timer Interrupt Flag 2 ($1025)
TOF EQU BIT7
RTIF EQU BIT6
PAOVF EQU BIT5
PAIF EQU BIT4
* PACTL - Pulse Accumulator Control Register ($1026)
DDRA7 EQU BIT7
PAEN EQU BIT6
PAMOD EQU BIT5
PEDGE EQU BIT4
DDRA3 EQU BIT3
I4O5 EQU BIT2
RTR1 EQU BIT1
RTR0 EQU BIT0
*-----------------------------------
* Serial Peripheral Interface (SPI)
* SPCR - Serial Peripheral Control Register ($1028)
SPIE EQU BIT7
SPE EQU BIT6
DWOM EQU BIT5
MSTR EQU BIT4
CPOL EQU BIT3
CPHA EQU BIT2
SPR1 EQU BIT1
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 7
SPR0 EQU BIT0
* SPSR - Serial Peripheral Status Register ($1029)
SPIF EQU BIT7
WCOL EQU BIT6
MODF EQU BIT4
*---------------------------------------
* Serial Communications Interface (SCI)
* BAUD - Baud Rate Register ($102b)
TCLR EQU BIT7
SCP2 EQU BIT6
SCP1 EQU BIT5
SCP0 EQU BIT4
RCKB EQU BIT3
SCR2 EQU BIT2
SCR1 EQU BIT1
SCR0 EQU BIT0
* SCCR1 - Serial Communications Control Register 1 ($102b)
R8 EQU BIT7
T8 EQU BIT6
M EQU BIT4
WAKE EQU BIT3
* SCCR2 - Serial Communications Control Register 2 ($102c)
TIE EQU BIT7
TCIE EQU BIT6
RIE EQU BIT5
ILIE EQU BIT4
TE EQU BIT3
RE EQU BIT2
RWU EQU BIT1
SBK EQU BIT0
* SCSR - Serial Communications Status Register ($102e)
TDRE EQU BIT7
TC EQU BIT6
RDRF EQU BIT5
IDLE EQU BIT4
OR EQU BIT3
NF EQU BIT2
FE EQU BIT1
* SCDR - Serial Communications Data Register ($102f)
R7T7 EQU BIT7
R6T6 EQU BIT6
R5T5 EQU BIT5
R4T4 EQU BIT4
R3T3 EQU BIT3
R2T2 EQU BIT2
R1T1 EQU BIT1
R0T0 EQU BIT0
*-----------------------------------
* Analog-to-Digital (A2D) Converter
* ADCTL - Analog-to-Digital Control Status Register ($1030)
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 8
CCF EQU BIT7
SCAN EQU BIT5
MULT EQU BIT4
CD EQU BIT3
CC EQU BIT2
CB EQU BIT1
CA EQU BIT0
* BPROT - Block Protect Register ($1035)
PTCON EQU BIT4
BPRT3 EQU BIT3
BPRT2 EQU BIT2
BPRT1 EQU BIT1
BRPT0 EQU BIT0
* EPROG - EPROM Programming Control Register ($1036)
MBE EQU BIT7
ELAT EQU BIT6
EXCOL EQU BIT5
EXROW EQU BIT4
T1 EQU BIT2
T0 EQU BIT1
PGM EQU BIT0
* OPTION - System Configuration Options Register ($1039)
ADPU EQU BIT7
CSEL EQU BIT6
IRQE EQU BIT5
DLY EQU BIT4
CME EQU BIT3
CR1 EQU BIT1
CR0 EQU BIT0
* PPROG - EPROM and EEPROM Programming Control Register
. ($103b)
ODD EQU BIT7
EVEN EQU BIT6
BYTE EQU BIT4
ROW EQU BIT3
ERASE EQU BIT2
EELAT EQU BIT1
EPGM EQU BIT0
* HPRIO - Highest Priority I Bit Interrupt and Miscellaneous
. Register ($103c)
RBOOT EQU BIT7
SMOD EQU BIT6
MDA EQU BIT5
IRVNE EQU BIT4
PSEL3 EQU BIT3
PSEL2 EQU BIT2
PSEL1 EQU BIT1
PSEL0 EQU BIT0
* INIT - RAM and I/O Mapping Register ($103d)
RAM3 EQU BIT7
RAM2 EQU BIT6
RAM1 EQU BIT5
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 9
RAM0 EQU BIT4
REG3 EQU BIT3
REG2 EQU BIT2
REG1 EQU BIT1
REG0 EQU BIT0
* CONFIG - System Configuration Register ($103f)
NOSEC EQU BIT3
NOCOP EQU BIT2
ROMON EQU BIT1
EEON EQU BIT0
#include "registers.asm"
#include "buffalo.asm"
* Buffalo subroutine jumptable addresses
* Each location in the jump table contains an appropriate JMP
. instruction.
* To use, just JSR to the jump table address that you want to
. use.
Buffalo_utljmp_base org $ffa0
UPCASE rmb JUMPSIZE ; Convert character to
. uppercase
WCHEK rmb JUMPSIZE ; Test character for
. whitespace
DCHEK rmb JUMPSIZE ; Check character for
. delimiter
INITDEV rmb JUMPSIZE ; Initialize I/O device
INPUT rmb JUMPSIZE ; Read I/O device
OUTPUT rmb JUMPSIZE ; Write I/O device
OUTLHLF rmb JUMPSIZE ; Convert left nibble to
. ASCII and output
OUTRHLF rmb JUMPSIZE ; Convert right nibble to
. ASCII and output
OUTA rmb JUMPSIZE ; Output ASCII character
OUT1BYT rmb JUMPSIZE ; Convert binary byte to 2
. ASCII characters and output
OUT1BSP rmb JUMPSIZE ; Convert binary byte to 2
. ASCII characters and output followed by space
OUT2BSP rmb JUMPSIZE ; Convert 2 consecutive
. binary bytes to 4 ASCII characters and output followed by
. space
OUTCRLF rmb JUMPSIZE ; Output ASCII carriage
. return followed by line feed
OUTSTRG rmb JUMPSIZE ; Output ASCII string until
. end of transmission ($04)
OUTSTRG0 rmb JUMPSIZE ; Same as OUTSTRG except
. leading carriage return and line feed is skipped
INCHAR rmb JUMPSIZE ; Input ASCII character and
. echo back
VECINIT rmb JUMPSIZE ; Initialize RAM interrupt
. vector table
* Buffalo interrupt vector jumptable addresses
* Each location in the jump table contains an appropriate JMP
. instruction.
* To use, store the address of your ISR at the jumptable
. address+1.
Buffalo_intjmp_base org $00c4
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 10
JSCI rmb JUMPSIZE ; Serial Communications
. Interface
JSPI rmb JUMPSIZE ; Serial Peripheral Interface
JPAIE rmb JUMPSIZE ; Pulse Accumulator input
. edge
JPAO rmb JUMPSIZE ; Pulse Accumulator overflow
JTOF rmb JUMPSIZE ; Timer overflow
JTI4C5 rmb JUMPSIZE ; Timer input capture 4 /
. output compare 5
JTOC4 rmb JUMPSIZE ; Timer output compare 4
JTOC3 rmb JUMPSIZE ; Timer output compare 3
JTOC2 rmb JUMPSIZE ; Timer output compare 2
JTOC1 rmb JUMPSIZE ; Timer output compare 1
JTIC3 rmb JUMPSIZE ; Timer input capture 3
JTIC2 rmb JUMPSIZE ; Timer input capture 2
JTIC1 rmb JUMPSIZE ; Timer input capture 1
JRTI rmb JUMPSIZE ; Real-time interrupt
JIRQ rmb JUMPSIZE ; IRQ pin (maskable)
JXIRQ rmb JUMPSIZE ; XIRQ pin (nonmaskable)
JSWI rmb JUMPSIZE ; Software Interrupt
JILLOP rmb JUMPSIZE ; Illegal opcode trap
JCOP rmb JUMPSIZE ; Computer Operating Properly
. watchdog failure
JCLM rmb JUMPSIZE ; Clock monitor failure
* Pseudo-vector addresses in RAM, within the above jumptable
. entries.
* The +1's are to skip over the JMP instruction opcode.
PVSCI equ JSCI+1 ; Serial Communications
. Interface
PVSPI equ JSPI+1 ; Serial Peripheral Interface
PVPAIE equ JPAIE+1 ; Pulse Accumulator input
. edge
PVPAO equ JPAO+1 ; Pulse Accumulator overflow
PVTOF equ JTOF+1 ; Timer overflow
PVTI4C5 equ JTI4C5+1 ; Timer input capture 4 /
. output compare 5
PVTOC4 equ JTOC4+1 ; Timer output compare 4
PVTOC3 equ JTOC3+1 ; Timer output compare 3
PVTOC2 equ JTOC2+1 ; Timer output compare 2
PVTOC1 equ JTOC1+1 ; Timer output compare 1
PVTIC3 equ JTIC3+1 ; Timer input capture 3
PVTIC2 equ JTIC2+1 ; Timer input capture 2
PVTIC1 equ JTIC1+1 ; Timer input capture 1
PVRTI equ JRTI+1 ; Real-time interrupt
PVIRQ equ JIRQ+1 ; IRQ pin (maskable)
PVXIRQ equ JXIRQ+1 ; XIRQ pin (nonmaskable)
PVSWI equ JSWI+1 ; Software Interrupt
PVILLOP equ JILLOP+1 ; Illegal opcode trap
PVCOP equ JCOP+1 ; Computer Operating Properly
. watchdog failure
PVCLM equ JCLM+1 ; Clock monitor failure
#include "buffalo.asm"
org JTOC1
00DF 7E 22 34 jmp myISR
org $2000
2000 7E 21 63 jmp main
#include "lcd.asm"
glyph_table equ 0 ; No glyph table
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 11
xcoord: rmb 1
ycoord: rmb 1
mydel: rmb 2
main:
2163 BD 20 03 jsr init_LCD
2166 86 0C ldaa #DISP_ONOFF|D_DISP ; No blink/cursor
2168 BD 21 05 jsr send_cmd
216B 86 00 ldaa #0 ; Write an "A" in
. upper-left corner of display.
216D C6 00 ldab #0
216F B7 21 5F staa xcoord
2172 F7 21 60 stab ycoord
2175 86 41 ldaa #'A
2177 BD 21 0C jsr write_lcd
217A CE FF FF ldx #$ffff ; Set delay to 65,535 timer ticks.
217D FF 21 61 stx mydel
* Initialize timer alarm setting
2180 FC 10 0E ldd TCNTH ; Load current timer value
2183 F3 21 61 addd mydel ; Add my delay
2186 FD 10 16 std TOC1H ; Set timer output compare 1
2189 CE 21 EF ldx #msg3 ; Some diagnostic messages
218C BD FF C7 jsr outstrg
218F CE 10 0E ldx #TCNTH
2192 BD FF C1 jsr out2bsp
2195 CE 22 07 ldx #msg4
2198 BD FF C7 jsr outstrg
219B CE 10 16 ldx #TOC1H
219E BD FF C1 jsr out2bsp
21A1 BD FF C4 jsr outcrlf
* Turn on TOC1 interrupt
* ldx #myISR ; My ISR
* stx JTOC1+1 ; Store in jumptable for TOC1.
21A4 CE 22 1B ldx #msg5
21A7 BD FF C7 jsr outstrg
21AA CE 00 E0 ldx #JTOC1+1
21AD BD FF C1 jsr out2bsp
21B0 BD FF C4 jsr outcrlf
21B3 86 80 ldaa #OC1I ; Select output compare 1 interrupt
21B5 B7 10 22 staa TMSK1 ; Set it in timer interrupt mask 1
. register
21B8 B7 10 23 staa TFLG1 ; Clear OC1 flag
21BB 0E cli ; Enable interrupts
21BC CE 00 00 inf: ldx #0
21BF BD 21 1D jsr dloop
21C2 CE 21 DC ldx #msg2
21C5 BD FF C7 jsr outstrg
21C8 20 F2 bra inf
21CA 57 65 27 72 msg1: fcc "We're in the ISR."
. 21CE 65 20 69 6E
. 21D2 20 20 68 65
. 21D6 20 49 53 52
. 21DA 2E
21DB 04 fcb EOT
21DC 4D 61 69 6E msg2: fcc "Main loop running."
. 21E0 20 6C 6F 6F
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 12
. 21E4 70 20 72 75
. 21E8 6E 6E 69 6E
. 21EC 67 2E
21EE 04 fcb EOT
21EF 49 6E 69 74 msg3: fcc "Initial timer setting: "
. 21F3 69 61 6C 20
. 21F7 74 69 6D 65
. 21FB 72 20 73 65
. 21FF 74 74 69 20
. 2203 67 3A 20
2206 04 fcb EOT
2207 54 4F 43 31 msg4: fcc "TOC1 alarm set to: "
. 220B 20 61 6C 61
. 220F 72 6D 20 73
. 2213 65 74 20 74
. 2217 6F 3A 20
221A 04 fcb EOT
221B 4A 75 6D 70 msg5: fcc "Jumptable entry set to: "
. 221F 74 61 62 6C
. 2223 65 20 65 6E
. 2227 74 72 79 20
. 222B 73 65 74 20
. 222F 74 6F 3A 20
2233 04 fcb EOT
myISR:
2234 FC 10 16 ldd TOC1 ; Load current alarm setting
2237 F3 21 61 addd mydel ; Add my delay
223A FD 10 16 std TOC1 ; Set timer output compare 1
* ldx #msg1
* jsr outstrg
223D B6 21 5F ldaa xcoord
2240 F6 21 60 ldab ycoord
2243 BD 20 90 jsr gotoxy
2246 86 20 ldaa #SPACE
2248 BD 21 0C jsr write_lcd
224B F6 21 60 ldab ycoord
224E 5C incb
224F C1 04 cmpb #4
2251 26 12 bne yok
2253 C6 00 ldab #0
2255 F7 21 60 stab ycoord
2258 B6 21 5F ldaa xcoord
225B 4C inca
225C 81 14 cmpa #20
225E 26 02 bne xok
2260 86 00 ldaa #0
2262 B7 21 5F xok: staa xcoord
* jsr adjust_delay
2265 F7 21 60 yok: stab ycoord
2268 B6 21 5F ldaa xcoord
226B F6 21 60 ldab ycoord
226E BD 20 90 jsr gotoxy
2271 86 41 ldaa #'A
2273 BD 21 0C jsr write_lcd
2276 CE 10 23 ldx #TFLG1
2279 1C 00 80 bset 0,x OC1F
227C 3B rti
ADDR B1 B2 B3 B4 F:\public_html\EEL4746\programs\library\ PAGE 13
adjust_delay:
227D FC 21 61 ldd mydel
2280 44 lsra ; shift D right
2281 56 rorb
2282 FD 21 61 std mydel
2285 CE 21 61 ldx #mydel
2288 BD FF C1 jsr out2bsp
228B BD FF C4 jsr outcrlf
228E 39 rts
Symbol Table
MSG3 21EF
MSG4 2207
ALL1S 00FF
MSG5 221B
CLR_HOM 0001
CA 0001
SEND_CMD 2105
CB 0002
MULT 0010
ETB 0017
CC 0004
CD 0008
NOCOP 0004
STORE_GLYPH 2137
CR 000D
INCHAR FFCD
EDG1A 0010
EDG1B 0020
ETX 0003
RL_RIGHT 0004
BPRT1 0002
BPRT2 0004
BPRT3 0008
ID_INC 0002
STAF 0080
ENDSTR 00FF
OPTION 1039
STAI 0040
ROW4_END 0067
CONFIG 103F
US 001F
TMPX 208F
PORTCL 1005
FOC1 0080
FOC2 0040
OUTA FFB8
FOC3 0020
PLS 0004
FOC4 0010
BRPT0 0001
FOC5 0008
PVTOC1 00E0
PVTOC2 00DD
PVTOC3 00DA
PAMOD 0020
PVTOC4 00D7
EDG2A 0004
EDG2B 0008
B_BLINK 0001
YOK 2265
PVCOP 00FB
ROW1_START 0000
DDRAM_ADDRSET 0080
Symbol Table F:\public_html\EEL4746\programs\library\ PAGE 14
WRITE_LCD 210C
VT 000B
CPOL 0008
EM 0019
PEDGE 0010
PAOVF 0020
NOMORE 20EB
PAOVI 0020
TIE 0080
EDG3A 0001
EVEN 0040
IDLE 0010
EDG3B 0002
EXROW 0010
PVRTI 00EC
FE 0002
RTIF 0040
FF 000C
M 0010
PVTIC1 00E9
PVTIC2 00E6
RTII 0040
PCL0 0001
PVTIC3 00E3
PCL1 0002
I4O5 0004
PCL2 0004
COPRST 103A
TI4O5H 101E
R6T6 0040
PCL3 0008
SOH 0001
PCL4 0010
CR0 0001
PCL5 0020
CR1 0002
PCL6 0040
TI4O5L 101F
PCL7 0080
BEL 0007
PVIRQ 00EF
JCLM 00FD
FS 001C
ROW3_END 0027
PACTL 1026
REG0 0001
PAEN 0040
EDG4A 0040
REG1 0002
EDG4B 0080
INIT 103D
REG2 0004
DLE 0010
REG3 0008
R3T3 0008
ROW_LENGTH 0014
TCTL1 1020
DLOOP 211D
TCTL2 1021
SPIE 0080
SPIF 0080
SPE 0040
LSTRL 20D7
EGA 0002
WAIT_LCD 2113
Symbol Table F:\public_html\EEL4746\programs\library\ PAGE 15
TI4O5 101E
LCD_OUT 20A9
PVSPI 00C8
R0T0 0001
TDRE 0080
GS 001D
OUTLHLF FFB2
SFLAG 0080
TMSK1 1022
ZFLAG 0004
JUMPSIZE 0003
ODD 0080
DLY 0010
TMSK2 1024
SHOW_GLYPHS 2155
STORE_GLYPHS 2121
N_2LINES 0008
SPACE 0020
RAM0 0010
RAM1 0020
BIT10 0004
RAM2 0040
SCCR1 102C
BIT11 0008
UPCASE FFA0
RAM3 0080
SCCR2 102D
BIT12 0010
BIT13 0020
CAN 0018
IC1F 0004
BIT14 0040
MYDEL 2161
BIT15 0080
IC1I 0004
NEXTGL 2125
EEON 0001
OC1D3 0008
OUTRHLF FFB5
OC1D4 0010
PIOC 1002
OC1D5 0020
OC1D6 0040
OC1D7 0080
BAUD 102B
DCHEK FFA6
NEXTROW 2145
LCD_CTL B5F0
OC1D 100D
PR0 0001
JTOC1 00DF
PR1 0002
OC1F 0080
JTOC2 00DC
EXCOL 0020
INIT_LCD 2003
ROW2_END 0053
ENT_MOD 0004
JTOC3 00D9
LCD_BASE B5F0
JTOC4 00D6
IC2F 0002
OC1I 0080
EPGM 0001
RWU 0002
Symbol Table F:\public_html\EEL4746\programs\library\ PAGE 16
IC2I 0002
TIC1H 1010
OC1M 100C
SC_SHIFT 0008
CWOM 0020
PA0 0001
PA1 0002
ADCTL 1030
TIC1L 1011
GLYPH_TABLE 0000
PA2 0004
PA3 0008
PA4 0010
DL_8BIT 0010
PA5 0020
JCOP 00FA
VECINIT FFD0
OUTCRLF FFC4
PA6 0040
PA7 0080
BUFFALO_INTJMP_BASE00C4
CCF 0080
EPROG 1036
OC2F 0040
IC3F 0001
OC2I 0040
TOC1H 1016
SHIFT_LEFT 20FE
TFLG1 1023
TFLG2 1025
IC3I 0001
TIC2H 1012
MAIN 2163
TOC1L 1017
PTCON 0010
PAIF 0010
PB0 0001
TCIE 0040
PB1 0002
TIC2L 1013
JTIC1 00E8
PB2 0004
JTIC2 00E5
PAII 0010
PB3 0008
JTIC3 00E2
SCP0 0010
PB4 0010
SCP1 0020
PB5 0020
JRTI 00EB
SCP2 0040
PB6 0040
PB7 0080
SBK 0001
PVPAO 00CE
OC3F 0020
CFORC 100B
IC4F 0008
OC3I 0020
TOC2H 1018
JIRQ 00EE
PSEL0 0001
PSEL1 0002
IC4I 0008
Symbol Table F:\public_html\EEL4746\programs\library\ PAGE 17
TIC3H 1014
PSEL2 0004
TOC2L 1019
PSEL3 0008
PC0 0001
PVXIRQ 00F2
PC1 0002
TIC3L 1015
PC2 0004
PC3 0008
ROW1_END 0013
PC4 0010
PC5 0020
PC6 0040
PC7 0080
TOF 0080
NOSEC 0008
R7T7 0080
TOI 0080
PVTOF 00D1
PVSCI 00C5
CSEL 0040
STX 0002
RIE 0020
OC4F 0010
SUB 001A
LF 000A
MBE 0080
OC4I 0010
TOC3H 101A
JSPI 00C7
ROW4_START 0054
F_5X10DOTS 0004
TOC3L 101B
CFLAG 0001
PD0 0001
ILIE 0010
PD1 0002
R4T4 0010
PD2 0004
PD3 0008
SCR0 0001
PD4 0010
OUT1BSP FFBE
SCR1 0002
PD5 0020
XFLAG 0040
SCR2 0004
RBASE 1000
YCOORD 2160
OC5F 0008
S_SHIFT 0001
R1T1 0002
DDRA3 0008
RDRF 0020
MODF 0010
OC5I 0008
OIN 0008
TOC4H 101C
HNDS 0010
LCD_DAT B5F1
DDRA7 0080
TOC4L 101D
PE0 0001
PE1 0002
Symbol Table F:\public_html\EEL4746\programs\library\ PAGE 18
PE2 0004
PE3 0008
PE4 0010
PE5 0020
PE6 0040
PE7 0080
SMOD 0040
ROMON 0002
MDA 0020
JTI4C5 00D3
JILLOP 00F7
NF 0004
TCLR 0080
WCHEK FFA3
RTR0 0001
WORDSIZE 0002
RTR1 0002
HPRIO 103C
SCAN 0020
PVPAIE 00CB
DC1 0011
DC2 0012
D_DISP 0004
PVSWI 00F5
DC3 0013
OUTSTRG0 FFCA
DC4 0014
WAIT_LOOP 2117
RET_HOM 0002
LOCMAP 203F
OL2 0040
ENQ 0005
IFLAG 0010
OL3 0010
DDRC0 0001
OL4 0004
DDRC1 0002
TAB 0009
OL5 0001
DDRC2 0004
SCSR 102E
DDRC3 0008
LCD_FIX 20CE
ADPU 0080
DDRC4 0010
SPR0 0001
DDRC5 0020
SPR1 0002
CPHA 0004
DDRC6 0040
DDRC7 0080
DISP_ONOFF 0008
DWOM 0020
MYISR 2234
LCD_AD1 20C0
LCD_AD2 20C4
IRVNE 0010
OR 0008
LCD_AD3 20C8
ADR1 1031
LCD_AD4 20CC
ADR2 1032
ROW3_START 0014
JPAO 00CD
BUFFALO_UTLJMP_BASEFFA0
Symbol Table F:\public_html\EEL4746\programs\library\ PAGE 19
ADR3 1033
SET_LOC 20EE
ADR4 1034
JXIRQ 00F1
LCDSTR 20D5
OM2 0080
OM3 0020
DDRD0 0001
OM4 0008
DDRD1 0002
OM5 0002
DDRD2 0004
EOT 0004
CD_SHIFT 0010
DDRD3 0008
TCNT 100E
ELAT 0040
DDRD4 0010
DDRD5 0020
PORTA 1000
PORTB 1004
PORTC 1003
ACK 0006
PORTD 1008
PORTE 100A
BIT0 0001
BIT1 0002
BIT2 0004
SYN 0016
BIT3 0008
BIT4 0010
JTOF 00D0
JSCI 00C4
PGM 0001
BIT5 0020
BIT6 0040
BIT7 0080
XOK 2262
DDRC 1007
BIT8 0001
DDRD 1009
BIT9 0002
NAK 0015
I4O5F 0008
MSTR 0010
I4O5I 0008
WCOL 0040
GOTOXY 2090
PRINTIT 2156
R8 0080
PPROG 103B
HFLAG 0020
OC1M3 0008
TCNTH 100E
OC1M4 0010
SCDR 102F
PVTI4C5 00D4
OUTSTRG FFC7
RBOOT 0080
OC1M5 0020
OC1M6 0040
DEL 007F
XCOORD 215F
PVILLOP 00F8
VFLAG 0002
Symbol Table F:\public_html\EEL4746\programs\library\ PAGE 20
OC1M7 0080
TCNTL 100F
SPSR 1029
BPROT 1035
RCKB 0008
RE 0004
TOC1 1016
R5T5 0020
TOC2 1018
FUNC_SET 0020
TOC3 101A
ERASE 0004
TOC4 101C
TOC5 101E
C_CURSOR 0002
INPUT FFAC
CLEAR_DISP 20F7
PACNT 1027
OUT2BSP FFC1
RS 001E
R2T2 0004
JPAIE 00CA
RES0 1001
OUT1BYT FFBB
ROW 0008
RES1 1006
RES2 1037
RES3 1038
RES4 103E
IRQE 0020
INVB 0001
ROW2_START 0040
T0 0002
T1 0004
SPCR 1028
SI 000F
WAKE 0008
PVCLM 00FE
JSWI 00F4
BYTE 0010
INF 21BC
ESC 001B
T8 0040
SO 000E
BF 0080
OUTPUT FFAF
EELAT 0002
NUL 0000
TIC1 1010
READ_LOC 2038
TIC2 1012
TIC3 1014
TIC4 101E
CME 0008
CGRAM_ADDRSET 0040
TC 0040
TE 0008
INITDEV FFA9
NFLAG 0008
BS 0008
MSG1 21CA
ADJUST_DELAY 227D
MSG2 21DC
ADDRSIZE 0002
SPDR 102A