ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 1
*------------------------------------------------------------
. ---
* timertest3.asm - Program to test timer routines.
*
* This version uses the general routine setup_periodic_alarm
* defined in "timer.asm" to set 5 periodic alarms with
. varying
* periods. Each of them controls a different letter which
. moves
* across the LCD screen, each at a different speed.
*------------------------------------------------------------
. ----
*#include "ascii.asm"
#include "registers.asm"
rbase EQU $1000 ; Default base
. address of HC11 I/O control registers
*------------------------------------------------------------
. ----------
* Internal HC11 I/O registers defined as addresses starting
. from rbase.
*------------------------------------------------------------
. ----------
* Parallel I/O registers.
PORTA EQU rbase+$00 ; Port A Data Register
res0 EQU rbase+$01 ; Reserved register #0
PIOC EQU rbase+$02 ; Parallel I/O Control
. Register
PORTC EQU rbase+$03 ; Port C Data Register
PORTB EQU rbase+$04 ; Port B Data Register
PORTCL EQU rbase+$05 ; Port C Latched Register
res1 EQU rbase+$06 ; Reserved register #1
DDRC EQU rbase+$07 ; Port C Data Direction
. Register
PORTD EQU rbase+$08 ; Port D Data Register
DDRD EQU rbase+$09 ; Port D Data Direction
. Register
PORTE EQU rbase+$0a ; Port E Data Register
* Timer system registers.
CFORC EQU rbase+$0b ; Timer Compare Force
. Register
OC1M EQU rbase+$0c ; Output Compare 1 Mask
. Register
OC1D EQU rbase+$0d ; Output Compare 1 Data
. Register
TCNTH EQU rbase+$0e ; Timer Counter Register High
. (MSB)
TCNTL EQU rbase+$0f ; Timer Counter Register Low
. (LSB)
TCNT EQU TCNTH ; Timer Counter Register
. (word)
TIC1H EQU rbase+$10 ; Timer Input Capture 1
. Register High (MSB)
TIC1L EQU rbase+$11 ; Timer Input Capture 1
. Register Low (LSB)
TIC1 EQU TIC1H ; Timer Input Capture 1
. Register (word)
TIC2H EQU rbase+$12 ; Timer Input Capture 2
. Register High (MSB)
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 2
TIC2L EQU rbase+$13 ; Timer Input Capture 2
. Register Low (LSB)
TIC2 EQU TIC2H ; Timer Input Capture 2
. Register (word)
TIC3H EQU rbase+$14 ; Timer Input Capture 3
. Register High (MSB)
TIC3L EQU rbase+$15 ; Timer Input Capture 3
. Register Low (LSB)
TIC3 EQU TIC3H ; Timer Input Capture 3
. Register (word)
TOC1H EQU rbase+$16 ; Timer Output Compare 1
. Register High (MSB)
TOC1L EQU rbase+$17 ; Timer Output Compare 1
. Register Low (LSB)
TOC1 EQU TOC1H ; Timer Output Compare 1
. Register (word)
TOC2H EQU rbase+$18 ; Timer Output Compare 2
. Register High (MSB)
TOC2L EQU rbase+$19 ; Timer Output Compare 2
. Register Low (LSB)
TOC2 EQU TOC2H ; Timer Output Compare 2
. Register (word)
TOC3H EQU rbase+$1a ; Timer Output Compare 3
. Register High (MSB)
TOC3L EQU rbase+$1b ; Timer Output Compare 3
. Register Low (LSB)
TOC3 EQU TOC3H ; Timer Output Compare 3
. Register (word)
TOC4H EQU rbase+$1c ; Timer Output Compare 4
. Register High (MSB)
TOC4L EQU rbase+$1d ; Timer Output Compare 4
. Register Low (LSB)
TOC4 EQU TOC4H ; Timer Output Compare 4
. Register (word)
TI4O5H EQU rbase+$1e ; Timer Input Capture 4/
. Output Compare 5 Register High (MSB)
TI4O5L EQU rbase+$1f ; Timer Input Capture 4/
. Output Compare 5 Register Low (LSB)
TI4O5 EQU TI4O5H ; Timer Input Capture 4/
. Output Compare 5 Register (word)
TIC4 EQU TI4O5 ; Timer Input Capture 4
. (word)
TOC5 EQU TI4O5 ; Timer Output Compare 5
. (word)
TCTL1 EQU rbase+$20 ; Timer Control Register 1
TCTL2 EQU rbase+$21 ; Timer Control Register 2
TMSK1 EQU rbase+$22 ; Timer Interrupt Mask 1
. Register
TFLG1 EQU rbase+$23 ; Timer Interrupt Flag 1
TMSK2 EQU rbase+$24 ; Timer Interrupt Mask 2
. Register
TFLG2 EQU rbase+$25 ; Timer Interrupt Flag 2
PACTL EQU rbase+$26 ; Pulse Accumulator Control
. Register
PACNT EQU rbase+$27 ; Pulse Accumulator Count
. Register
* Serial Peripheral Interface (SPI) registers.
SPCR EQU rbase+$28 ; Serial Peripheral Control
. Register
SPSR EQU rbase+$29 ; Serial Peripheral Status
. Register
SPDR EQU rbase+$2a ; Serial Peripheral Data I/O
. Register
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 3
* Serial Communications Interface (SCI) registers.
BAUD EQU rbase+$2b ; Baud Rate Register
SCCR1 EQU rbase+$2c ; Serial Communications
. Control Register 1
SCCR2 EQU rbase+$2d ; Serial Communications
. Control Register 2
SCSR EQU rbase+$2e ; Serial Communications
. Status Register
SCDR EQU rbase+$2f ; Serial Communications Data
. Register
* Analog-to-Digital (A2D) system registers.
ADCTL EQU rbase+$30 ; Analog-to-Digital Control
. Status Register
ADR1 EQU rbase+$31 ; Analog-to-Digital Results
. Register 1
ADR2 EQU rbase+$32 ; Analog-to-Digital Results
. Register 2
ADR3 EQU rbase+$33 ; Analog-to-Digital Results
. Register 3
ADR4 EQU rbase+$34 ; Analog-to-Digital Results
. Register 4
* Miscellaneous control and configuration registers.
BPROT EQU rbase+$35 ; Block Protect Register
EPROG EQU rbase+$36 ; EPROM Programming Control
. Register (711E20 only)
res2 EQU rbase+$37 ; Reserved register #2
res3 EQU rbase+$38 ; Reserved register #3
OPTION EQU rbase+$39 ; System Configuration
. Options Register
COPRST EQU rbase+$3a ; Arm/Reset COP Timer
. Circuitry Register
PPROG EQU rbase+$3b ; EPROM and EEPROM
. Programming Control Register
HPRIO EQU rbase+$3c ; Highest Priority I Bit
. Interrupt and Miscellaneous Reigster
INIT EQU rbase+$3d ; RAM and I/O Mapping
. Register
res4 EQU rbase+$3e ; Reserved register #4
CONFIG EQU rbase+$3f ; System Configuration
. Register
*----------------------------------------------------------
* Individual register bits.
* See datasheet for full descriptions. (Index on pp.38-43.)
*
* To use these, use BSET, BCLR, BRSET, BRCLR instructions
* on the appropriate register address and with an
* appropriate mask (logical OR of bits that you want).
*----------------------------------------------------------
*----------------
* Parallel Ports
* PORTA - Port A Data Register ($1000)
PA7 EQU BIT7
PA6 EQU BIT6
PA5 EQU BIT5
PA4 EQU BIT4
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 4
PA3 EQU BIT3
PA2 EQU BIT2
PA1 EQU BIT1
PA0 EQU BIT0
* PIOC - Parallel I/O Control Register ($1002)
STAF EQU BIT7
STAI EQU BIT6
CWOM EQU BIT5
HNDS EQU BIT4
OIN EQU BIT3
PLS EQU BIT2
EGA EQU BIT1
INVB EQU BIT0
* PORTC - Port C Data Register ($1003)
PC7 EQU BIT7
PC6 EQU BIT6
PC5 EQU BIT5
PC4 EQU BIT4
PC3 EQU BIT3
PC2 EQU BIT2
PC1 EQU BIT1
PC0 EQU BIT0
* PORTB - Port B Data Register ($1004)
PB7 EQU BIT7
PB6 EQU BIT6
PB5 EQU BIT5
PB4 EQU BIT4
PB3 EQU BIT3
PB2 EQU BIT2
PB1 EQU BIT1
PB0 EQU BIT0
* PORTCL - Port C Latched Register ($1005)
PCL7 EQU BIT7
PCL6 EQU BIT6
PCL5 EQU BIT5
PCL4 EQU BIT4
PCL3 EQU BIT3
PCL2 EQU BIT2
PCL1 EQU BIT1
PCL0 EQU BIT0
* DDRC - Port C Data Direction Register ($1007)
DDRC7 EQU BIT7
DDRC6 EQU BIT6
DDRC5 EQU BIT5
DDRC4 EQU BIT4
DDRC3 EQU BIT3
DDRC2 EQU BIT2
DDRC1 EQU BIT1
DDRC0 EQU BIT0
* PORTD - Port D Data Register ($1008)
PD5 EQU BIT5
PD4 EQU BIT4
PD3 EQU BIT3
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 5
PD2 EQU BIT2
PD1 EQU BIT1
PD0 EQU BIT0
* DDRD - Port D Data Register ($1009)
DDRD5 EQU BIT5
DDRD4 EQU BIT4
DDRD3 EQU BIT3
DDRD2 EQU BIT2
DDRD1 EQU BIT1
DDRD0 EQU BIT0
* PORTE - Port E Data Register ($100a)
PE7 EQU BIT7
PE6 EQU BIT6
PE5 EQU BIT5
PE4 EQU BIT4
PE3 EQU BIT3
PE2 EQU BIT2
PE1 EQU BIT1
PE0 EQU BIT0
*-----------------
* Timer facility
* CFORC - Timer Compare Force Register ($100b)
FOC1 EQU BIT7
FOC2 EQU BIT6
FOC3 EQU BIT5
FOC4 EQU BIT4
FOC5 EQU BIT3
* OC1M - Output Compare 1 Mask Register ($100c)
OC1M7 EQU BIT7
OC1M6 EQU BIT6
OC1M5 EQU BIT5
OC1M4 EQU BIT4
OC1M3 EQU BIT3
* OC1D - Output Compare 1 Data Register ($100d)
OC1D7 EQU BIT7
OC1D6 EQU BIT6
OC1D5 EQU BIT5
OC1D4 EQU BIT4
OC1D3 EQU BIT3
* TCTL1 - Timer Control Register 1 ($1020)
OM2 EQU BIT7
OL2 EQU BIT6
OM3 EQU BIT5
OL3 EQU BIT4
OM4 EQU BIT3
OL4 EQU BIT2
OM5 EQU BIT1
OL5 EQU BIT0
* TCTL2 - Timer Control Register 2 ($1021)
EDG4B EQU BIT7
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 6
EDG4A EQU BIT6
EDG1B EQU BIT5
EDG1A EQU BIT4
EDG2B EQU BIT3
EDG2A EQU BIT2
EDG3B EQU BIT1
EDG3A EQU BIT0
* TMSK1 - Timer Interrupt Mask 1 Register ($1022)
OC1I EQU BIT7
OC2I EQU BIT6
OC3I EQU BIT5
OC4I EQU BIT4
I4O5I EQU BIT3
OC5I EQU I4O5I
IC4I EQU I4O5I
IC1I EQU BIT2
IC2I EQU BIT1
IC3I EQU BIT0
* TFLG1 - Timer Interrupt Flag 1 ($1023)
OC1F EQU BIT7
OC2F EQU BIT6
OC3F EQU BIT5
OC4F EQU BIT4
I4O5F EQU BIT3
OC5F EQU I4O5F
IC4F EQU I4O5F
IC1F EQU BIT2
IC2F EQU BIT1
IC3F EQU BIT0
* TMSK2 - Timer Interrupt Mask 2 Register ($1024)
TOI EQU BIT7
RTII EQU BIT6
PAOVI EQU BIT5
PAII EQU BIT4
PR1 EQU BIT1
PR0 EQU BIT0
* TFLG2 - Timer Interrupt Flag 2 ($1025)
TOF EQU BIT7
RTIF EQU BIT6
PAOVF EQU BIT5
PAIF EQU BIT4
* PACTL - Pulse Accumulator Control Register ($1026)
DDRA7 EQU BIT7
PAEN EQU BIT6
PAMOD EQU BIT5
PEDGE EQU BIT4
DDRA3 EQU BIT3
I4O5 EQU BIT2
RTR1 EQU BIT1
RTR0 EQU BIT0
*-----------------------------------
* Serial Peripheral Interface (SPI)
* SPCR - Serial Peripheral Control Register ($1028)
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 7
SPIE EQU BIT7
SPE EQU BIT6
DWOM EQU BIT5
MSTR EQU BIT4
CPOL EQU BIT3
CPHA EQU BIT2
SPR1 EQU BIT1
SPR0 EQU BIT0
* SPSR - Serial Peripheral Status Register ($1029)
SPIF EQU BIT7
WCOL EQU BIT6
MODF EQU BIT4
*---------------------------------------
* Serial Communications Interface (SCI)
* BAUD - Baud Rate Register ($102b)
TCLR EQU BIT7 ; Clear Baud Rate Counter Bit (test)
SCP2 EQU BIT6 ; SCI Baud Rate Prescaler Select Bits
SCP1 EQU BIT5 ; .
SCP0 EQU BIT4 ; .
RCKB EQU BIT3 ; SCI Baud Rate Clock Check Bit
SCR2 EQU BIT2 ; SCI Baud Rate Select Bits
SCR1 EQU BIT1 ; .
SCR0 EQU BIT0 ; .
* SCCR1 - Serial Communications Control Register 1 ($102b)
R8 EQU BIT7 ; Ninth bit in received data, in 8
. data bit mode (M=1)
T8 EQU BIT6 ; Ninth bit in transmitted data, in 9
. data bit mode (M=1)
M EQU BIT4 ; Mode bit; 0 = 8 data bits, 1 = 9
. data bits.
WAKE EQU BIT3 ; Wakeup by Address Mark/Idle bit
* SCCR2 - Serial Communications Control Register 2 ($102c)
TIE EQU BIT7 ; Transmit Interrupt Enable; SCI
. Interrupt requested when TDRE flag gets set
TCIE EQU BIT6 ; Transmit Complete Interrupt Enable;
. SCI Interrupt when TC status flag set
RIE EQU BIT5 ; Receiver Interrupt Enable; SCI int.
. when RDRF or OR status flag is set
ILIE EQU BIT4 ; Idle-Line Interrupt Enable; SCI
. int. when IDLE status flag is set
TE EQU BIT3 ; Transmitter Enable. Rising edge
. outputs 1 idle character.
RE EQU BIT2 ; Receiver Enable.
RWU EQU BIT1 ; Receiver Wakeup Control Bit. 1 =
. Wakeup enabled, receiver interrupts inhibited
SBK EQU BIT0 ; Send Break character
* SCSR - Serial Communications Status Register ($102e)
TDRE EQU BIT7 ; Transmit Data Register Emptpy Flag
TC EQU BIT6 ; Transmit Complete Flag
RDRF EQU BIT5 ; Receive Data Register Full Flag
IDLE EQU BIT4 ; Idle Line Detected Flag
OR EQU BIT3 ; Overrun Error Flag
NF EQU BIT2 ; Noise Error Flag
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 8
FE EQU BIT1 ; Framing Error Flag
* SCDR - Serial Communications Data Register ($102f)
R7T7 EQU BIT7 ; Bit 7 of byte received/transmitted
R6T6 EQU BIT6 ; .
R5T5 EQU BIT5 ; .
R4T4 EQU BIT4 ; .
R3T3 EQU BIT3 ; .
R2T2 EQU BIT2 ; .
R1T1 EQU BIT1 ; .
R0T0 EQU BIT0 ; Bit 0 of byte received/transmitted
*-----------------------------------
* Analog-to-Digital (A2D) Converter
* ADCTL - Analog-to-Digital Control Status Register ($1030)
CCF EQU BIT7
SCAN EQU BIT5
MULT EQU BIT4
CD EQU BIT3
CC EQU BIT2
CB EQU BIT1
CA EQU BIT0
* BPROT - Block Protect Register ($1035)
PTCON EQU BIT4
BPRT3 EQU BIT3
BPRT2 EQU BIT2
BPRT1 EQU BIT1
BRPT0 EQU BIT0
* EPROG - EPROM Programming Control Register ($1036)
MBE EQU BIT7
ELAT EQU BIT6
EXCOL EQU BIT5
EXROW EQU BIT4
T1 EQU BIT2
T0 EQU BIT1
PGM EQU BIT0
* OPTION - System Configuration Options Register ($1039)
ADPU EQU BIT7
CSEL EQU BIT6
IRQE EQU BIT5
DLY EQU BIT4
CME EQU BIT3
CR1 EQU BIT1
CR0 EQU BIT0
* PPROG - EPROM and EEPROM Programming Control Register
. ($103b)
ODD EQU BIT7
EVEN EQU BIT6
BYTE EQU BIT4
ROW EQU BIT3
ERASE EQU BIT2
EELAT EQU BIT1
EPGM EQU BIT0
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 9
* HPRIO - Highest Priority I Bit Interrupt and Miscellaneous
. Register ($103c)
RBOOT EQU BIT7
SMOD EQU BIT6
MDA EQU BIT5
IRVNE EQU BIT4
PSEL3 EQU BIT3
PSEL2 EQU BIT2
PSEL1 EQU BIT1
PSEL0 EQU BIT0
* INIT - RAM and I/O Mapping Register ($103d)
RAM3 EQU BIT7
RAM2 EQU BIT6
RAM1 EQU BIT5
RAM0 EQU BIT4
REG3 EQU BIT3
REG2 EQU BIT2
REG1 EQU BIT1
REG0 EQU BIT0
* CONFIG - System Configuration Register ($103f)
NOSEC EQU BIT3
NOCOP EQU BIT2
ROMON EQU BIT1
EEON EQU BIT0
#include "registers.asm"
#include "buffalo.asm"
* Buffalo subroutine jumptable addresses
* Each location in the jump table contains an appropriate JMP
. instruction.
* To use, just JSR to the jump table address that you want to
. use.
Buffalo_utljmp_base org $ffa0
UPCASE rmb JUMPSIZE ; Convert character to
. uppercase
WCHEK rmb JUMPSIZE ; Test character for
. whitespace
DCHEK rmb JUMPSIZE ; Check character for
. delimiter
INITDEV rmb JUMPSIZE ; Initialize I/O device
INPUT rmb JUMPSIZE ; Read I/O device
OUTPUT rmb JUMPSIZE ; Write I/O device
OUTLHLF rmb JUMPSIZE ; Convert left nibble to
. ASCII and output
OUTRHLF rmb JUMPSIZE ; Convert right nibble to
. ASCII and output
OUTA rmb JUMPSIZE ; Output ASCII character
OUT1BYT rmb JUMPSIZE ; Convert binary byte to 2
. ASCII characters and output
OUT1BSP rmb JUMPSIZE ; Convert binary byte to 2
. ASCII characters and output followed by space
OUT2BSP rmb JUMPSIZE ; Convert 2 consecutive
. binary bytes to 4 ASCII characters and output followed by
. space
OUTCRLF rmb JUMPSIZE ; Output ASCII carriage
. return followed by line feed
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 10
OUTSTRG rmb JUMPSIZE ; Output ASCII string until
. end of transmission ($04)
OUTSTRG0 rmb JUMPSIZE ; Same as OUTSTRG except
. leading carriage return and line feed is skipped
INCHAR rmb JUMPSIZE ; Input ASCII character and
. echo back
VECINIT rmb JUMPSIZE ; Initialize RAM interrupt
. vector table
* Buffalo interrupt vector jumptable addresses
* Each location in the jump table contains an appropriate JMP
. instruction.
* To use, store the address of your ISR at the jumptable
. address+1.
Buffalo_intjmp_base org $00c4
JSCI rmb JUMPSIZE ; Serial Communications
. Interface
JSPI rmb JUMPSIZE ; Serial Peripheral Interface
JPAIE rmb JUMPSIZE ; Pulse Accumulator input
. edge
JPAO rmb JUMPSIZE ; Pulse Accumulator overflow
JTOF rmb JUMPSIZE ; Timer overflow
JTI4C5 rmb JUMPSIZE ; Timer input capture 4 /
. output compare 5
JTOC4 rmb JUMPSIZE ; Timer output compare 4
JTOC3 rmb JUMPSIZE ; Timer output compare 3
JTOC2 rmb JUMPSIZE ; Timer output compare 2
JTOC1 rmb JUMPSIZE ; Timer output compare 1
JTIC3 rmb JUMPSIZE ; Timer input capture 3
JTIC2 rmb JUMPSIZE ; Timer input capture 2
JTIC1 rmb JUMPSIZE ; Timer input capture 1
JRTI rmb JUMPSIZE ; Real-time interrupt
JIRQ rmb JUMPSIZE ; IRQ pin (maskable)
JXIRQ rmb JUMPSIZE ; XIRQ pin (nonmaskable)
JSWI rmb JUMPSIZE ; Software Interrupt
JILLOP rmb JUMPSIZE ; Illegal opcode trap
JCOP rmb JUMPSIZE ; Computer Operating Properly
. watchdog failure
JCLM rmb JUMPSIZE ; Clock monitor failure
* Pseudo-vector addresses in RAM, within the above jumptable
. entries.
* The +1's are to skip over the JMP instruction opcode.
PVSCI equ JSCI+1 ; Serial Communications
. Interface
PVSPI equ JSPI+1 ; Serial Peripheral Interface
PVPAIE equ JPAIE+1 ; Pulse Accumulator input
. edge
PVPAO equ JPAO+1 ; Pulse Accumulator overflow
PVTOF equ JTOF+1 ; Timer overflow
PVTI4C5 equ JTI4C5+1 ; Timer input capture 4 /
. output compare 5
PVTOC4 equ JTOC4+1 ; Timer output compare 4
PVTOC3 equ JTOC3+1 ; Timer output compare 3
PVTOC2 equ JTOC2+1 ; Timer output compare 2
PVTOC1 equ JTOC1+1 ; Timer output compare 1
PVTIC3 equ JTIC3+1 ; Timer input capture 3
PVTIC2 equ JTIC2+1 ; Timer input capture 2
PVTIC1 equ JTIC1+1 ; Timer input capture 1
PVRTI equ JRTI+1 ; Real-time interrupt
PVIRQ equ JIRQ+1 ; IRQ pin (maskable)
PVXIRQ equ JXIRQ+1 ; XIRQ pin (nonmaskable)
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 11
PVSWI equ JSWI+1 ; Software Interrupt
PVILLOP equ JILLOP+1 ; Illegal opcode trap
PVCOP equ JCOP+1 ; Computer Operating Properly
. watchdog failure
PVCLM equ JCLM+1 ; Clock monitor failure
#include "buffalo.asm"
org $2000
2000 7E 23 B9 jmp main
#include "lcd.asm"
*#include "keypad.asm"
#include "timer.asm"
*#include "buffalo.asm" ; For SCI routines OUTSTRG0 and
. OUTCRLF
* Print debug message pointed to by X
printmsg:
2161 BD FF CA jsr OUTSTRG0
2164 BD FF C4 jsr OUTCRLF
2167 39 rts
mycrlf:
2168 36 psha
2169 86 0D LDAA #CR
216B BD FF AF JSR OUTPUT
216E 86 0A LDAA #LF
2170 BD FF AF JSR OUTPUT
2173 32 pula
2174 39 RTS
* Print current values of all registers.
printregs:
2175 36 psha ; Store all registers
2176 07 tpa
2177 B7 22 66 staa ccr
217A 32 pula
217B B7 22 5C staa accA
217E F7 22 5D stab accB
2181 FD 22 5E std accD
2184 FF 22 60 stx regIX
2187 18 FF 22 62 sty regIY
218B 3C pshx
218C 36 psha
218D CE 22 67 ldx #aeq
2190 BD FF C7 jsr outstrg
2193 CE 22 5C ldx #accA
2196 BD FF BE jsr out1bsp
2199 CE 22 6A ldx #beq
219C BD FF CA jsr outstrg0
219F CE 22 5D ldx #accB
21A2 BD FF BE jsr out1bsp
21A5 CE 22 6D ldx #deq
21A8 BD FF CA jsr outstrg0
21AB CE 22 5E ldx #accD
21AE BD FF C1 jsr out2bsp
21B1 CE 22 70 ldx #xeq
21B4 BD FF CA jsr outstrg0
21B7 CE 22 60 ldx #regIX
21BA BD FF C1 jsr out2bsp
21BD CE 22 73 ldx #yeq
21C0 BD FF CA jsr outstrg0
21C3 CE 22 62 ldx #regIY
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 12
21C6 BD FF C1 jsr out2bsp
21C9 CE 22 76 ldx #ccreq
21CC BD FF CA jsr outstrg0
21CF CE 22 66 ldx #ccr
21D2 BD FF BE jsr out1bsp
21D5 BD FF C4 jsr outcrlf
21D8 B6 22 66 ldaa ccr
21DB 06 tap
21DC 32 pula
21DD 38 pulx
21DE 39 rts
* Print current value of A accumulator.
21DF B7 22 5C printA: staa accA
21E2 36 psha
21E3 3C pshx
21E4 CE 22 5C ldx #accA
21E7 BD FF BE jsr out1bsp
21EA 38 pulx
21EB 32 pula
21EC 39 rts
21ED F7 22 5D printB: stab accB
21F0 36 psha
21F1 3C pshx
21F2 CE 22 5D ldx #accB
21F5 BD FF BE jsr out1bsp
21F8 38 pulx
21F9 32 pula
21FA 39 rts
21FB FD 22 5E printD: std accD
21FE 36 psha
21FF 3C pshx
2200 CE 22 5E ldx #accD
2203 BD FF C1 jsr out2bsp
2206 38 pulx
2207 32 pula
2208 39 rts
2209 FF 22 60 printX: stx regIX
220C 36 psha
220D 3C pshx
220E CE 22 60 ldx #regIX
2211 BD FF C1 jsr out2bsp
2214 38 pulx
2215 32 pula
2216 39 rts
2217 18 FF 22 62 printY: sty regIY
221B 36 psha
221C 3C pshx
221D CE 22 62 ldx #regIY
2220 BD FF C1 jsr out2bsp
2223 38 pulx
2224 32 pula
2225 18 FE 22 62 ldy regIY
2229 39 rts
222A 18 FF 22 62 printS: sty regIY
222E 18 30 tsy
2230 18 08 iny
2232 18 FF 22 64 sty regSP
2236 18 FE 22 62 ldy regIY
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 13
223A 36 psha
223B 3C pshx
223C 18 3C pshy
223E CE 22 64 ldx #regSP
2241 BD FF C1 jsr out2bsp
2244 18 38 puly
2246 38 pulx
2247 32 pula
2248 39 rts
printCCR:
2249 36 psha
224A 07 tpa
224B B7 22 66 staa ccr
224E 3C pshx
224F CE 22 66 ldx #ccr
2252 BD FF BE jsr out1bsp
2255 38 pulx
2256 B6 22 66 ldaa ccr
2259 06 tap
225A 32 pula
225B 39 rts
accA: rmb 1
accB: rmb 1
accD: rmb 2
regIX: rmb 2
regIY: rmb 2
regSP: rmb 2
ccr: rmb 1
2267 41 3D aeq: fcc "A="
2269 04 fcb EOT
226A 42 3D beq: fcc "B="
226C 04 fcb EOT
226D 44 3D deq: fcc "D="
226F 04 fcb EOT
2270 58 3D xeq: fcc "X="
2272 04 fcb EOT
2273 59 3D yeq: fcc "Y="
2275 04 fcb EOT
2276 43 43 52 3D ccreq: fcc "CCR="
227A 04 fcb EOT
* Wait for user to hit enter
227B 36 pause: psha
227C BD FF CD jsr inchar
227F 32 pula
2280 39 rts
#include "debug.asm"
*------------------------------------------------------------
. ---------------------------------------
* Subroutine: setup_periodic_alarm
* Purpose:
* Arrange for an alarm to go off at regular intervals,
. and call a specific subroutine every
* time it does. Uses the HC11's built-in Timer Output
. Compare facility. Supports up to 5
* independent alarms. User is responsible for doing
. the CLI to enable interrupts (either
* before or after calling this subroutine).
* Inputs:
* A = Alarm number, 0-4. (Corresponding to output
. compare functions OC1-OC5.)
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 14
* X = Pointer to subroutine to invoke (not an ISR).
* Y = Alarm period in timer ticks, 0-65535.
* Side effects:
* Timer output compare TOC(A+1) is set up to call
. subroutine at X.
* All registers are trashed.
* Stack layout:
* SP-> MEM[SP+0] (empty)
* Y-> MEM[SP+1:SP+2] local variable "Offset" (16-
. bit table offset, used in several places)
* MEM[SP+2:SP+3] local variable "Pseudo" (16-
. bit pointer to pseudo-vector)
* MEM[SP+3] local variable "CCR" (8-bit
. condition code register value when called)
* ...
*------------------------------------------------------------
. ---------------------------------------
* First, declare frame pointer offsets for local variables:
lOffset: equ 0 ; For offsets
. calculated from alarm numbers.
lPseudo: equ lOffset+2 ; For pointer to
. pseudo-vector address.
lCCR: equ lPseudo+2 ; For preserving
. caller's condition code register.
lPeriod: equ lCCR+1 ; For preserving
. caller's Y / period of alarm.
lSub: equ lPeriod+2 ; For preserving
. caller's X / pointer to user subroutine.
lAlarm: equ lSub+2 ; For preserving
. caller's A / alarm number.
sLocals: equ lAlarm+1 ; Total space
. occupied by local variables.
* Error messages.
2281 41 6C 61 72 alarm_too_big: fcc "Alarm number is too big."
. 2285 6D 20 6E 75
. 2289 6D 00 65 72
. 228D 20 69 73 20
. 2291 74 6F 6F 00
. 2295 62 69 67 2E
2299 04 fcb EOT
* The actual subroutine starts here.
setup_periodic_alarm:
* Save arguments, reserve space for local variables, and set
. up frame pointer.
229A 36 psha ; Stack variable lAlarm <-
. alarm number A.
229B 3C pshx ; Stack variable lSub <-
. subroutine pointer X.
229C 18 3C pshy ; Stack variable lPeriod <-
. alarm period Y.
229E 07 tpa ; Copy caller's predicate
. bits (CCR) to A.
229F 36 psha ; Stack variable lCCR <-
. caller's predicates.
22A0 18 30 tsy ; Let Y point to top of stack
. (lCCR).
22A2 18 8F xgdy ; Put frame pointer Y into D.
22A4 83 00 04 subd #lCCR ; Adjust it to make space for
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 15
. additional locals above lCCR. (lOffset, lPseudo)
22A7 18 8F xgdy ; Put frame pointer back into
. Y.
22A9 18 35 tys ; Move stack pointer above
. locals frame, in case we want to call subroutines.
* Do some error checking on our input arguments.
22AB 18 A6 09 ldaa lAlarm,y ; A = Alarm number.
22AE 81 04 cmpa #4 ; Max possible alarm number.
22B0 23 09 bls spa4 ; If that or lower, we're OK.
22B2 CE 22 81 ldx #alarm_too_big ; Select error message: Alarm
. is too big.
22B5 BD FF C7 jsr outstrg ; Print error message to SCI.
22B8 7E 23 29 jmp spa3 ; Exit from subroutine
. without really doing anything.
spa4:
* Disable interrupts before we start changing anything.
22BB 0F sei ; Mask interrupts while we're
. rearranging things.
* First, we calculate the pseudo-vector address in Buffalo's
. jumptable that we'll need to set.
22BC 18 A6 09 ldaa lAlarm,y ; A = Alarm number.
22BF C6 03 ldab #JUMPSIZE ; B = Size of a jump
. instruction.
22C1 3D mul ; D = Offset to the jumptable
. entry we want
22C2 18 ED 00 std lOffset,y ; Store it in lOffset local
. variable.
22C5 CC 00 E0 ldd #PVTOC1 ; Point D at last TOC
. jumptable pseudo-vector entry.
22C8 18 A3 00 subd lOffset,y ; Subtract the lOffset we
. saved earlier.
22CB 18 ED 02 std lPseudo,y ; Store D in lPseudo local
. variable.
* Next, find the address of the appropriate ISR.
22CE 18 E6 09 ldab lAlarm,y ; Load alarm number.
22D1 58 lslb ; Double to get a word
. offset.
22D2 4F clra ; Clear MSB of D; effectively
. transfers B->D.
22D3 18 ED 00 std lOffset,y ; Store in lOffset local
. variable.
22D6 C3 23 9B addd #TOC_ISRs ; Add base address of TOC ISR
. table.
22D9 8F xgdx ; Transfer TOC ISR table
. entry pointer to X.
22DA EC 00 ldd 0,x ; Transfer TOC ISR pointer to
. D.
* Now, store the ISR address in the pseudo-vector location.
22DC CD EE 02 ldx lPseudo,y ; Load pseudo-vector pointer
. we computed in previous section.
22DF ED 00 std 0,x ; Store TOC ISR pointer at
. pseudo-vector location. This sets up the vector.
* Figure out where to store our subroutine pointer.
22E1 18 EC 00 ldd lOffset,y ; Load offset we computed
. earlier.
22E4 C3 23 AF addd #sub1 ; Add base of subroutine
. pointer table.
22E7 8F xgdx ; X now points to subroutine
. pointer table entry.
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 16
* Store the subroutine pointer there.
22E8 18 EC 07 ldd lSub,y ; Load pointer to the actual
. subroutine into D.
22EB ED 00 std 0,x ; Store it in the subroutine
. pointer table entry.
* Now, compute the appropriate mask bit to select OCa in the
. TMSK1 and TFLG1 registers.
22ED C6 80 ldab #OC1I ; Bit mask for OC1I register
. bit. (Also is OC1F.)
22EF 18 A6 09 ldaa lAlarm,y ; This is the alarm number 0-
. 4 we pushed earlier.
22F2 27 04 spa0: beq spa1 ; If it's 0, the mask we have
. now is the right one.
22F4 54 lsrb ; Shift the mask right one
. position (go to next OC)
22F5 4A deca ; Subtract 1 from alarm
. number.
22F6 20 FA bra spa0 ; Keep looping.
spa1:
* The following code actually enables the interrupts on
. Output Compare #a to occur.
22F8 F7 10 23 stab TFLG1 ; Storing "1" turns OFF bit
. OCaF in TFLG1 (clears state of OCaF flag).
22FB FA 10 22 orab TMSK1 ; This prevents the next line
. from turning off other OCxI bits.
22FE F7 10 22 stab TMSK1 ; Turns on bit OCaI in TMSK1
. (enables interrupt OCaI).
* Remember the period, for use by the ISR.
2301 18 EC 00 ldd lOffset,y ; Load offset computed
. earlier.
2304 C3 23 A5 addd #per1 ; Add to base of table of
. periods.
2307 8F xgdx ; Point X at the entry we
. want.
2308 18 EC 05 ldd lPeriod,y ; Load the period.
230B ED 00 std 0,x ; Store X in the table of
. periods.
* Finally, we set the initial OCa alarm time relative to the
. present time.
230D 18 EC 00 ldd lOffset,y ; Load offset which we
. computed earlier.
2310 F3 10 16 addd TOC1 ; Add to base of TOC
. registers to point to TOCa.
2313 8F xgdx ; Put the pointer into regIX.
2314 FC 10 0E ldd TCNT ; Load the present system
. timer value.
2317 18 E3 05 addd lPeriod,y ; Add it to the alarm period
. that we saved earlier.
231A ED 00 std 0,x ; Store it in the appropriate
. TOCa register. (This line sets the initial alarm trigger
. time.)
* Finally, if alarm 4 (OC5) was selected, we have to
. configure pin PA3 as OC5 rather than IC4.
231C 18 A6 09 ldaa lAlarm,y ; Load A with the alarm
. number.
231F 81 04 cmpa #4 ; Was it alarm #4?
. (Representing OC5.)
2321 26 06 bne spa2 ; If not, then don't...
2323 CE 10 26 ldx #PACTL ; Select PACTL
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 17
. register.
2326 1D 00 04 bclr 0,x I4O5 ; Clear the I4/O5 bit
. (select OC5 rather than IC4 for pin PA3).
spa2:
* Throw away all the locals, restore stack pointer and the I
. bit. Don't bother restoring any other registers.
2329 18 A6 04 spa3: ldaa lCCR,y ; Load caller's CCR (really
. we just care about I).
232C 06 tap ; Transfer it to the real
. CCR. (This may re-enable interrupts, if they were enabled in
. caller.)
232D 18 8F xgdy ; Move frame pointer into D.
232F C3 00 0A addd #sLocals ; Bump it up past all the
. locals. (Including pushed registers.)
2332 18 8F xgdy ; Transfer it back to Y.
2334 18 35 tys ; And from there back to the
. stack pointer. Now it's safe to return.
2336 39 rts ; Return from setup_periodic_
. alarm subroutine.
*------------------------------------------------------------
. ------------
* Interrupt Service Routines that may be set up by setup_
. periodic_alarm.
*------------------------------------------------------------
. ------------
ISR_TOC1:
2337 FC 10 16 ldd TOC1 ; Get current TOC1 alarm time.
233A F3 23 A5 addd per1 ; Add the period for this periodic
. timer.
233D FD 10 16 std TOC1 ; Store it as the new alarm time.
2340 FE 23 AF ldx sub1 ; Load first subroutine address.
2343 AD 00 jsr 0,x ; Jump to that subroutine.
2345 86 80 ldaa #OC1F ; Select OC1F flag (in TFLG1
. register).
2347 B7 10 23 staa TFLG1 ; Write 1 to OC1F in TFLG1 to turn
. off OC1F, which resets TOC1.
234A 3B rti ; Return from ISR_TOC1.
ISR_TOC2:
234B FC 10 18 ldd TOC2 ; Get current TOC2 alarm time.
234E F3 23 A7 addd per2 ; Add the period for this periodic
. timer.
2351 FD 10 18 std TOC2 ; Store it as the new alarm time.
2354 FE 23 B1 ldx sub2 ; Load 2nd subroutine address.
2357 AD 00 jsr 0,x ; Jump to that subroutine.
2359 86 40 ldaa #OC2F ; Select OC2F flag (in TFLG1
. register).
235B B7 10 23 staa TFLG1 ; Write 1 to OC2F in TFLG1 to turn
. off OC2F, which resets TOC2.
235E 3B rti ; Return from ISR_TOC2.
ISR_TOC3:
235F FC 10 1A ldd TOC3 ; Get current TOC3 alarm time.
2362 F3 23 A9 addd per3 ; Add the period for this periodic
. timer.
2365 FD 10 1A std TOC3 ; Store it as the new alarm time.
2368 FE 23 B3 ldx sub3 ; Load 3rd subroutine address.
236B AD 00 jsr 0,x ; Jump to that subroutine.
236D 86 20 ldaa #OC3F ; Select OC3F flag (in TFLG1
. register).
236F B7 10 23 staa TFLG1 ; Write 1 to OC3F in TFLG1 to turn
. off OC3F, which resets TOC3.
2372 3B rti ; Return from ISR_TOC3.
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 18
ISR_TOC4:
2373 FC 10 1C ldd TOC4 ; Get current TOC4 alarm time.
2376 F3 23 AB addd per4 ; Add the period for this periodic
. timer.
2379 FD 10 1C std TOC4 ; Store it as the new alarm time.
237C FE 23 B5 ldx sub4 ; Load 4th subroutine address.
237F AD 00 jsr 0,x ; Jump to that subroutine.
2381 86 10 ldaa #OC4F ; Select OC4F flag (in TFLG1
. register).
2383 B7 10 23 staa TFLG1 ; Write 1 to OC4F in TFLG1 to turn
. off OC4F, which resets TOC4.
2386 3B rti ; Return from ISR_TOC3.
ISR_TOC5:
2387 FC 10 1E ldd TOC5 ; Get current TOC5 alarm time.
238A F3 23 AD addd per5 ; Add the period for this periodic
. timer.
238D FD 10 1E std TOC5 ; Store it as the new alarm time.
2390 FE 23 B7 ldx sub5 ; Load 5th subroutine address.
2393 AD 00 jsr 0,x ; Jump to that subroutine.
2395 86 08 ldaa #OC5F ; Select OC5F flag (in TFLG1
. register).
2397 B7 10 23 staa TFLG1 ; Write 1 to OC5F in TFLG1 to turn
. off OC5F, which resets TOC5.
239A 3B rti ; Return from ISR_TOC5.
*------------------------------------------------------
* Persistent variables needed by setup_periodic_alarm.
*------------------------------------------------------
* Table of pointers to all of our ISRs for the TOC
. interrupts.
TOC_ISRs:
239B 23 37 fdb ISR_TOC1
239D 23 4B fdb ISR_TOC2
239F 23 5F fdb ISR_TOC3
23A1 23 73 fdb ISR_TOC4
23A3 23 87 fdb ISR_TOC5
* Programmers: Be sure to locate the below variable data
. region in RAM.
* Data region for remembering the periods for the 5 possible
. periodic alarms.
per1: rmb WORDSIZE ; Store here how many ticks
. OC1 takes.
per2: rmb WORDSIZE ; Ditto for OC2, etc.
per3: rmb WORDSIZE
per4: rmb WORDSIZE
per5: rmb WORDSIZE
* Data region for remembering the addresses of the
. subroutines to call upon alarm.
sub1: rmb WORDSIZE
sub2: rmb WORDSIZE
sub3: rmb WORDSIZE
sub4: rmb WORDSIZE
sub5: rmb WORDSIZE
#include "timer.asm"
glyph_table equ 0 ; No glyph table
SPINNER equ 5 ; Slowdown factor for all periodic
. timers
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 19
23B9 0F main: sei
23BA BD 20 03 jsr init_LCD
23BD 86 0C ldaa #DISP_ONOFF|D_DISP ; No blink/cursor
23BF BD 21 07 jsr send_cmd
23C2 86 05 ldaa #SPINNER
23C4 B7 24 25 staa acount
23C7 B7 24 4F staa bcount
23CA B7 24 79 staa ccount
23CD B7 24 A3 staa dcount
23D0 B7 24 CD staa ecount
23D3 86 00 ldaa #0 ; Select alarm #0
. (really this means OC1).
23D5 CE 24 26 ldx #suba ; Select subroutine
. "suba" (below).
23D8 18 CE 90 00 ldy #$9000 ; Select my delay
. value.
23DC BD 22 9A jsr setup_periodic_alarm ; Call mysub every
. mydel timer ticks.
23DF 86 01 ldaa #1 ; Select alarm #1
. (really this means OC2).
23E1 CE 24 50 ldx #subb ; Select subroutine
. "subb" (below).
23E4 18 CE B0 00 ldy #$b000 ; Select my delay
. value.
23E8 BD 22 9A jsr setup_periodic_alarm ; Call mysub every
. mydel timer ticks.
23EB 86 02 ldaa #2 ; Select alarm #2
. (really this means OC3).
23ED CE 24 7A ldx #subc ; Select subroutine
. "subc" (below).
23F0 18 CE D0 00 ldy #$d000 ; Select my delay
. value.
23F4 BD 22 9A jsr setup_periodic_alarm ; Call mysub every
. mydel timer ticks.
23F7 86 03 ldaa #3 ; Select alarm #3
. (really this means OC4).
23F9 CE 24 A4 ldx #subd ; Select subroutine
. "subd" (below).
23FC 18 CE F0 00 ldy #$f000 ; Select my delay
. value.
2400 BD 22 9A jsr setup_periodic_alarm ; Call mysub every
. mydel timer ticks.
2403 86 04 ldaa #4 ; Select alarm #4
. (really this means OC5).
2405 CE 24 CE ldx #sube ; Select subroutine
. "subd" (below).
2408 18 CE FF FF ldy #$ffff ; Select my delay
. value.
240C BD 22 9A jsr setup_periodic_alarm ; Call mysub every
. mydel timer ticks.
240F 0E cli ; Enable interrupts
2410 3E spin: wai
2411 7E 24 10 jmp spin
2414 00 xa: fcb 0
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 20
2415 00 xb: fcb 0
2416 00 xc: fcb 0
2417 00 xd: fcb 0
2418 00 xe: fcb 0
clear:
2419 86 20 ldaa #SPACE
241B BD 21 0E jsr write_lcd
incamod20:
241E 4C inca
241F 81 14 cmpa #20
2421 26 01 bne incamod20_end
2423 4F clra
2424 39 incamod20_end: rts
2425 00 acount: fcb 0
2426 7A 24 25 suba: dec acount
2429 26 23 bne return
242B B6 24 14 ldaa xa
242E C6 00 ldab #0
2430 BD 20 90 jsr gotoxy
2433 BD 24 19 jsr clear
2436 B6 24 14 ldaa xa
2439 BD 24 1E jsr incamod20
243C B7 24 14 staa xa
243F C6 00 ldab #0
2441 BD 20 90 jsr gotoxy
2444 86 41 ldaa #'A
2446 BD 21 0E jsr write_lcd
2449 86 05 ldaa #SPINNER
244B B7 24 25 staa acount
244E 39 return: rts
244F 00 bcount: fcb 0
2450 7A 24 4F subb: dec bcount
2453 26 F9 bne return
2455 B6 24 15 ldaa xb
2458 C6 01 ldab #1
245A BD 20 90 jsr gotoxy
245D BD 24 19 jsr clear
2460 B6 24 15 ldaa xb
2463 BD 24 1E jsr incamod20
2466 B7 24 15 staa xb
2469 C6 01 ldab #1
246B BD 20 90 jsr gotoxy
246E 86 42 ldaa #'B
2470 BD 21 0E jsr write_lcd
2473 86 05 ldaa #SPINNER
2475 B7 24 4F staa bcount
2478 39 rts
2479 00 ccount: fcb 0
247A 7A 24 79 subc: dec ccount
247D 26 CF bne return
247F B6 24 16 ldaa xc
ADDR B1 B2 B3 B4 X:\public_html\EEL4746\programs\library\ PAGE 21
2482 C6 02 ldab #2
2484 BD 20 90 jsr gotoxy
2487 BD 24 19 jsr clear
248A B6 24 16 ldaa xc
248D BD 24 1E jsr incamod20
2490 B7 24 16 staa xc
2493 C6 02 ldab #2
2495 BD 20 90 jsr gotoxy
2498 86 43 ldaa #'C
249A BD 21 0E jsr write_lcd
249D 86 05 ldaa #SPINNER
249F B7 24 79 staa ccount
24A2 39 rts
24A3 00 dcount: fcb 0
24A4 7A 24 A3 subd: dec dcount
24A7 26 A5 bne return
24A9 B6 24 17 ldaa xd
24AC C6 03 ldab #3
24AE BD 20 90 jsr gotoxy
24B1 BD 24 19 jsr clear
24B4 B6 24 17 ldaa xd
24B7 BD 24 1E jsr incamod20
24BA B7 24 17 staa xd
24BD C6 03 ldab #3
24BF BD 20 90 jsr gotoxy
24C2 86 44 ldaa #'D
24C4 BD 21 0E jsr write_lcd
24C7 86 05 ldaa #SPINNER
24C9 B7 24 A3 staa dcount
24CC 39 rts
24CD 00 ecount: fcb 0
24CE 7A 24 CD sube: dec ecount
24D1 26 25 bne rete
24D3 B6 24 18 ldaa xe
24D6 C6 03 ldab #3
24D8 BD 20 90 jsr gotoxy
24DB BD 24 19 jsr clear
24DE B6 24 18 ldaa xe
24E1 4A deca
24E2 2A 02 bpl okd
24E4 86 13 ldaa #19
24E6 B7 24 18 okd: staa xe
24E9 C6 03 ldab #3
24EB BD 20 90 jsr gotoxy
24EE 86 45 ldaa #'E
24F0 BD 21 0E jsr write_lcd
24F3 86 05 ldaa #SPINNER
24F5 B7 24 CD staa ecount
24F8 39 rete: rts
Symbol Table
Symbol Table X:\public_html\EEL4746\programs\library\ PAGE 22
ALL1S 00FF
CLR_HOM 0001
CA 0001
ETB 0017
SEND_CMD 2107
CB 0002
MULT 0010
CC 0004
CD 0008
NOCOP 0004
RETE 24F8
CR 000D
STORE_GLYPH 2139
INCHAR FFCD
EDG1A 0010
ETX 0003
EDG1B 0020
RL_RIGHT 0004
BPRT1 0002
BPRT2 0004
BPRT3 0008
ID_INC 0002
STAF 0080
ENDSTR 00FF
OPTION 1039
STAI 0040
US 001F
ROW4_END 0067
CONFIG 103F
TMPX 208F
PORTCL 1005
FOC1 0080
FOC2 0040
OUTA FFB8
FOC3 0020
PLS 0004
FOC4 0010
BRPT0 0001
FOC5 0008
PVTOC1 00E0
PVTOC2 00DD
PVTOC3 00DA
PAMOD 0020
PVTOC4 00D7
EDG2A 0004
EDG2B 0008
B_BLINK 0001
PVCOP 00FB
ROW1_START 0000
DDRAM_ADDRSET 0080
WRITE_LCD 210E
VT 000B
CPOL 0008
EM 0019
PEDGE 0010
PAOVF 0020
ALARM_TOO_BIG 2281
NOMORE 20EB
PAOVI 0020
TIE 0080
EDG3A 0001
EVEN 0040
IDLE 0010
EDG3B 0002
Symbol Table X:\public_html\EEL4746\programs\library\ PAGE 23
EXROW 0010
PER1 23A5
PER2 23A7
PVRTI 00EC
PER3 23A9
FE 0002
PER4 23AB
FF 000C
RTIF 0040
PER5 23AD
M 0010
PVTIC1 00E9
PVTIC2 00E6
RTII 0040
PCL0 0001
PVTIC3 00E3
PCL1 0002
I4O5 0004
PCL2 0004
COPRST 103A
TI4O5H 101E
SOH 0001
R6T6 0040
PCL3 0008
PCL4 0010
XA 2414
MYCRLF 2168
CR0 0001
PCL5 0020
XB 2415
CR1 0002
PCL6 0040
TI4O5L 101F
XC 2416
BEL 0007
PCL7 0080
XD 2417
PVIRQ 00EF
XE 2418
JCLM 00FD
FS 001C
ROW3_END 0027
BEQ 226A
PACTL 1026
REG0 0001
PAEN 0040
EDG4A 0040
REG1 0002
EDG4B 0080
INIT 103D
CCOUNT 2479
DLE 0010
REG2 0004
REG3 0008
R3T3 0008
ROW_LENGTH 0014
TCTL1 1020
DLOOP 211F
TCTL2 1021
XEQ 2270
SPIE 0080
SPIF 0080
SPE 0040
LSTRL 20D7
EGA 0002
Symbol Table X:\public_html\EEL4746\programs\library\ PAGE 24
WAIT_LCD 2115
TI4O5 101E
LCD_OUT 20A9
SPIN 2410
PVSPI 00C8
R0T0 0001
GS 001D
TDRE 0080
OUTLHLF FFB2
SFLAG 0080
TMSK1 1022
ZFLAG 0004
JUMPSIZE 0003
ODD 0080
DLY 0010
TMSK2 1024
SHOW_GLYPHS 2157
SETUP_PERIODIC_ALARM 229A
SPACE 0020
STORE_GLYPHS 2123
N_2LINES 0008
RAM0 0010
RAM1 0020
BIT10 0004
RAM2 0040
SCCR1 102C
BIT11 0008
UPCASE FFA0
RAM3 0080
SCCR2 102D
BIT12 0010
CAN 0018
BIT13 0020
IC1F 0004
BIT14 0040
BIT15 0080
IC1I 0004
NEXTGL 2127
EEON 0001
OC1D3 0008
OUTRHLF FFB5
OC1D4 0010
PIOC 1002
OC1D5 0020
OC1D6 0040
OC1D7 0080
BAUD 102B
DCHEK FFA6
NEXTROW 2147
LCD_CTL B5F0
OC1D 100D
PR0 0001
SLOCALS 000A
JTOC1 00DF
PR1 0002
OC1F 0080
JTOC2 00DC
EXCOL 0020
INIT_LCD 2003
ROW2_END 0053
ENT_MOD 0004
JTOC3 00D9
LCD_BASE B5F0
JTOC4 00D6
IC2F 0002
Symbol Table X:\public_html\EEL4746\programs\library\ PAGE 25
OC1I 0080
EPGM 0001
RWU 0002
IC2I 0002
TIC1H 1010
OC1M 100C
SC_SHIFT 0008
CWOM 0020
PA0 0001
PA1 0002
ADCTL 1030
TIC1L 1011
GLYPH_TABLE 0000
PA2 0004
PA3 0008
PA4 0010
SUB1 23AF
DL_8BIT 0010
PA5 0020
CLEAR 2419
SUB2 23B1
LCCR 0004
JCOP 00FA
VECINIT FFD0
OUTCRLF FFC4
PA6 0040
SUB3 23B3
PA7 0080
SUB4 23B5
BUFFALO_INTJMP_BASE 00C4
CCF 0080
SUB5 23B7
EPROG 1036
OC2F 0040
IC3F 0001
OC2I 0040
TOC1H 1016
SHIFT_LEFT 20FF
TFLG1 1023
TFLG2 1025
CCR 2266
IC3I 0001
TIC2H 1012
SUBA 2426
MAIN 23B9
TOC1L 1017
SUBB 2450
PTCON 0010
SUBC 247A
PAIF 0010
PB0 0001
SUBD 24A4
TCIE 0040
PB1 0002
TIC2L 1013
SUBE 24CE
JTIC1 00E8
PB2 0004
JTIC2 00E5
PAII 0010
PB3 0008
JTIC3 00E2
SCP0 0010
PB4 0010
SCP1 0020
Symbol Table X:\public_html\EEL4746\programs\library\ PAGE 26
PB5 0020
JRTI 00EB
SCP2 0040
PB6 0040
PB7 0080
SBK 0001
PVPAO 00CE
OC3F 0020
CFORC 100B
IC4F 0008
OC3I 0020
TOC2H 1018
JIRQ 00EE
PSEL0 0001
PSEL1 0002
IC4I 0008
TIC3H 1014
PSEL2 0004
TOC2L 1019
PSEL3 0008
LSUB 0007
PRINTREGS 2175
PC0 0001
PVXIRQ 00F2
PC1 0002
TIC3L 1015
PC2 0004
BCOUNT 244F
PC3 0008
ROW1_END 0013
PC4 0010
PC5 0020
PC6 0040
PC7 0080
TOF 0080
NOSEC 0008
R7T7 0080
TOI 0080
PRINTCCR 2249
PVTOF 00D1
PVSCI 00C5
STX 0002
CSEL 0040
SUB 001A
LF 000A
RIE 0020
OC4F 0010
MBE 0080
REGSP 2264
OC4I 0010
TOC3H 101A
JSPI 00C7
ROW4_START 0054
F_5X10DOTS 0004
TOC3L 101B
CFLAG 0001
PD0 0001
ISR_TOC1 2337
ILIE 0010
PD1 0002
ISR_TOC2 234B
R4T4 0010
PD2 0004
ISR_TOC3 235F
PD3 0008
Symbol Table X:\public_html\EEL4746\programs\library\ PAGE 27
ISR_TOC4 2373
LOFFSET 0000
SCR0 0001
PD4 0010
ISR_TOC5 2387
YEQ 2273
OUT1BSP FFBE
SCR1 0002
PD5 0020
XFLAG 0040
SCR2 0004
RBASE 1000
OC5F 0008
S_SHIFT 0001
R1T1 0002
DDRA3 0008
ACCA 225C
RDRF 0020
MODF 0010
OC5I 0008
OIN 0008
TOC4H 101C
ACCB 225D
HNDS 0010
ACCD 225E
LCD_DAT B5F1
DDRA7 0080
TOC4L 101D
PRINTMSG 2161
PE0 0001
PRINTA 21DF
PE1 0002
PRINTB 21ED
PE2 0004
PE3 0008
PRINTD 21FB
PE4 0010
PE5 0020
TOC_ISRS 239B
PE6 0040
PE7 0080
SMOD 0040
ROMON 0002
SPINNER 0005
MDA 0020
JTI4C5 00D3
JILLOP 00F7
NF 0004
TCLR 0080
WCHEK FFA3
RTR0 0001
WORDSIZE 0002
RTR1 0002
HPRIO 103C
PRINTS 222A
SCAN 0020
PVPAIE 00CB
DC1 0011
PRINTX 2209
DC2 0012
LPSEUDO 0002
PRINTY 2217
DC3 0013
D_DISP 0004
PVSWI 00F5
Symbol Table X:\public_html\EEL4746\programs\library\ PAGE 28
DC4 0014
OUTSTRG0 FFCA
WAIT_LOOP 2119
OKD 24E6
RET_HOM 0002
ECOUNT 24CD
LOCMAP 203F
CCREQ 2276
ENQ 0005
OL2 0040
IFLAG 0010
OL3 0010
DDRC0 0001
INCAMOD20 241E
TAB 0009
OL4 0004
DDRC1 0002
OL5 0001
DDRC2 0004
SCSR 102E
DDRC3 0008
LCD_FIX 20CE
ADPU 0080
DDRC4 0010
SPR0 0001
DDRC5 0020
SPR1 0002
CPHA 0004
DDRC6 0040
DDRC7 0080
DISP_ONOFF 0008
DWOM 0020
LCD_AD1 20C0
LCD_AD2 20C4
IRVNE 0010
OR 0008
LCD_AD3 20C8
ADR1 1031
SPA0 22F2
LCD_AD4 20CC
ADR2 1032
SPA1 22F8
ROW3_START 0014
JPAO 00CD
BUFFALO_UTLJMP_BASE FFA0
ADR3 1033
SPA2 2329
SET_LOC 20EE
ADR4 1034
SPA3 2329
SPA4 22BB
JXIRQ 00F1
LCDSTR 20D5
OM2 0080
OM3 0020
DDRD0 0001
OM4 0008
DDRD1 0002
EOT 0004
OM5 0002
DDRD2 0004
CD_SHIFT 0010
DDRD3 0008
TCNT 100E
ELAT 0040
Symbol Table X:\public_html\EEL4746\programs\library\ PAGE 29
DDRD4 0010
DDRD5 0020
PORTA 1000
ACOUNT 2425
PORTB 1004
ACK 0006
PORTC 1003
PORTD 1008
PORTE 100A
BIT0 0001
BIT1 0002
SYN 0016
BIT2 0004
BIT3 0008
BIT4 0010
JTOF 00D0
JSCI 00C4
PGM 0001
BIT5 0020
BIT6 0040
BIT7 0080
DDRC 1007
BIT8 0001
DDRD 1009
BIT9 0002
NAK 0015
I4O5F 0008
MSTR 0010
I4O5I 0008
WCOL 0040
GOTOXY 2090
RETURN 244E
PRINTIT 2158
R8 0080
PPROG 103B
HFLAG 0020
OC1M3 0008
TCNTH 100E
OC1M4 0010
SCDR 102F
PVTI4C5 00D4
OUTSTRG FFC7
RBOOT 0080
OC1M5 0020
DEL 007F
OC1M6 0040
PVILLOP 00F8
VFLAG 0002
OC1M7 0080
TCNTL 100F
SPSR 1029
DEQ 226D
BPROT 1035
RCKB 0008
RE 0004
LPERIOD 0005
TOC1 1016
R5T5 0020
TOC2 1018
FUNC_SET 0020
TOC3 101A
ERASE 0004
TOC4 101C
TOC5 101E
C_CURSOR 0002
Symbol Table X:\public_html\EEL4746\programs\library\ PAGE 30
INPUT FFAC
INCAMOD20_END 2424
CLEAR_DISP 20F7
LALARM 0009
PAUSE 227B
PACNT 1027
AEQ 2267
RS 001E
OUT2BSP FFC1
R2T2 0004
JPAIE 00CA
RES0 1001
OUT1BYT FFBB
ROW 0008
RES1 1006
RES2 1037
RES3 1038
RES4 103E
IRQE 0020
INVB 0001
ROW2_START 0040
T0 0002
T1 0004
SPCR 1028
SI 000F
WAKE 0008
PVCLM 00FE
JSWI 00F4
BYTE 0010
ESC 001B
SO 000E
T8 0040
BF 0080
OUTPUT FFAF
NUL 0000
EELAT 0002
TIC1 1010
DCOUNT 24A3
READ_LOC 2038
TIC2 1012
TIC3 1014
TIC4 101E
CME 0008
CGRAM_ADDRSET 0040
TC 0040
REGIX 2260
REGIY 2262
TE 0008
BS 0008
INITDEV FFA9
NFLAG 0008
ADDRSIZE 0002
SPDR 102A