ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 1 *------------------------------------------------------------ . ------ * timertest2.asm - Test timer capabilities of HC11 * * Move the letter "A" around the LCD screen, driven by . interrupts * from the HC11 Timer Output compare #1 function. This . version * Uses timer.asm to set up the timer for us. *------------------------------------------------------------ . ------ *#include "ascii.asm" #include "registers.asm" rbase EQU $1000 ; Default base . address of HC11 I/O control registers *------------------------------------------------------------ . ---------- * Internal HC11 I/O registers defined as addresses starting . from rbase. *------------------------------------------------------------ . ---------- * Parallel I/O registers. PORTA EQU rbase+$00 ; Port A Data Register res0 EQU rbase+$01 ; Reserved register #0 PIOC EQU rbase+$02 ; Parallel I/O Control . Register PORTC EQU rbase+$03 ; Port C Data Register PORTB EQU rbase+$04 ; Port B Data Register PORTCL EQU rbase+$05 ; Port C Latched Register res1 EQU rbase+$06 ; Reserved register #1 DDRC EQU rbase+$07 ; Port C Data Direction . Register PORTD EQU rbase+$08 ; Port D Data Register DDRD EQU rbase+$09 ; Port D Data Direction . Register PORTE EQU rbase+$0a ; Port E Data Register * Timer system registers. CFORC EQU rbase+$0b ; Timer Compare Force . Register OC1M EQU rbase+$0c ; Output Compare 1 Mask . Register OC1D EQU rbase+$0d ; Output Compare 1 Data . Register TCNTH EQU rbase+$0e ; Timer Counter Register High . (MSB) TCNTL EQU rbase+$0f ; Timer Counter Register Low . (LSB) TCNT EQU TCNTH ; Timer Counter Register . (word) TIC1H EQU rbase+$10 ; Timer Input Capture 1 . Register High (MSB) TIC1L EQU rbase+$11 ; Timer Input Capture 1 . Register Low (LSB) TIC1 EQU TIC1H ; Timer Input Capture 1 . Register (word) TIC2H EQU rbase+$12 ; Timer Input Capture 2 . Register High (MSB) TIC2L EQU rbase+$13 ; Timer Input Capture 2 ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 2 . Register Low (LSB) TIC2 EQU TIC2H ; Timer Input Capture 2 . Register (word) TIC3H EQU rbase+$14 ; Timer Input Capture 3 . Register High (MSB) TIC3L EQU rbase+$15 ; Timer Input Capture 3 . Register Low (LSB) TIC3 EQU TIC3H ; Timer Input Capture 3 . Register (word) TOC1H EQU rbase+$16 ; Timer Output Compare 1 . Register High (MSB) TOC1L EQU rbase+$17 ; Timer Output Compare 1 . Register Low (LSB) TOC1 EQU TOC1H ; Timer Output Compare 1 . Register (word) TOC2H EQU rbase+$18 ; Timer Output Compare 2 . Register High (MSB) TOC2L EQU rbase+$19 ; Timer Output Compare 2 . Register Low (LSB) TOC2 EQU TOC2H ; Timer Output Compare 2 . Register (word) TOC3H EQU rbase+$1a ; Timer Output Compare 3 . Register High (MSB) TOC3L EQU rbase+$1b ; Timer Output Compare 3 . Register Low (LSB) TOC3 EQU TOC3H ; Timer Output Compare 3 . Register (word) TOC4H EQU rbase+$1c ; Timer Output Compare 4 . Register High (MSB) TOC4L EQU rbase+$1d ; Timer Output Compare 4 . Register Low (LSB) TOC4 EQU TOC4H ; Timer Output Compare 4 . Register (word) TI4O5H EQU rbase+$1e ; Timer Input Capture 4/ . Output Compare 5 Register High (MSB) TI4O5L EQU rbase+$1f ; Timer Input Capture 4/ . Output Compare 5 Register Low (LSB) TI4O5 EQU TI4O5H ; Timer Input Capture 4/ . Output Compare 5 Register (word) TIC4 EQU TI4O5 ; Timer Input Capture 4 . (word) TOC5 EQU TI4O5 ; Timer Output Compare 5 . (word) TCTL1 EQU rbase+$20 ; Timer Control Register 1 TCTL2 EQU rbase+$21 ; Timer Control Register 2 TMSK1 EQU rbase+$22 ; Timer Interrupt Mask 1 . Register TFLG1 EQU rbase+$23 ; Timer Interrupt Flag 1 TMSK2 EQU rbase+$24 ; Timer Interrupt Mask 2 . Register TFLG2 EQU rbase+$25 ; Timer Interrupt Flag 2 PACTL EQU rbase+$26 ; Pulse Accumulator Control . Register PACNT EQU rbase+$27 ; Pulse Accumulator Count . Register * Serial Peripheral Interface (SPI) registers. SPCR EQU rbase+$28 ; Serial Peripheral Control . Register SPSR EQU rbase+$29 ; Serial Peripheral Status . Register SPDR EQU rbase+$2a ; Serial Peripheral Data I/O . Register ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 3 * Serial Communications Interface (SCI) registers. BAUD EQU rbase+$2b ; Baud Rate Register SCCR1 EQU rbase+$2c ; Serial Communications . Control Register 1 SCCR2 EQU rbase+$2d ; Serial Communications . Control Register 2 SCSR EQU rbase+$2e ; Serial Communications . Status Register SCDR EQU rbase+$2f ; Serial Communications Data . Register * Analog-to-Digital (A2D) system registers. ADCTL EQU rbase+$30 ; Analog-to-Digital Control . Status Register ADR1 EQU rbase+$31 ; Analog-to-Digital Results . Register 1 ADR2 EQU rbase+$32 ; Analog-to-Digital Results . Register 2 ADR3 EQU rbase+$33 ; Analog-to-Digital Results . Register 3 ADR4 EQU rbase+$34 ; Analog-to-Digital Results . Register 4 * Miscellaneous control and configuration registers. BPROT EQU rbase+$35 ; Block Protect Register EPROG EQU rbase+$36 ; EPROM Programming Control . Register (711E20 only) res2 EQU rbase+$37 ; Reserved register #2 res3 EQU rbase+$38 ; Reserved register #3 OPTION EQU rbase+$39 ; System Configuration . Options Register COPRST EQU rbase+$3a ; Arm/Reset COP Timer . Circuitry Register PPROG EQU rbase+$3b ; EPROM and EEPROM . Programming Control Register HPRIO EQU rbase+$3c ; Highest Priority I Bit . Interrupt and Miscellaneous Reigster INIT EQU rbase+$3d ; RAM and I/O Mapping . Register res4 EQU rbase+$3e ; Reserved register #4 CONFIG EQU rbase+$3f ; System Configuration . Register *---------------------------------------------------------- * Individual register bits. * See datasheet for full descriptions. (Index on pp.38-43.) * * To use these, use BSET, BCLR, BRSET, BRCLR instructions * on the appropriate register address and with an * appropriate mask (logical OR of bits that you want). *---------------------------------------------------------- *---------------- * Parallel Ports * PORTA - Port A Data Register ($1000) PA7 EQU BIT7 PA6 EQU BIT6 PA5 EQU BIT5 PA4 EQU BIT4 PA3 EQU BIT3 ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 4 PA2 EQU BIT2 PA1 EQU BIT1 PA0 EQU BIT0 * PIOC - Parallel I/O Control Register ($1002) STAF EQU BIT7 STAI EQU BIT6 CWOM EQU BIT5 HNDS EQU BIT4 OIN EQU BIT3 PLS EQU BIT2 EGA EQU BIT1 INVB EQU BIT0 * PORTC - Port C Data Register ($1003) PC7 EQU BIT7 PC6 EQU BIT6 PC5 EQU BIT5 PC4 EQU BIT4 PC3 EQU BIT3 PC2 EQU BIT2 PC1 EQU BIT1 PC0 EQU BIT0 * PORTB - Port B Data Register ($1004) PB7 EQU BIT7 PB6 EQU BIT6 PB5 EQU BIT5 PB4 EQU BIT4 PB3 EQU BIT3 PB2 EQU BIT2 PB1 EQU BIT1 PB0 EQU BIT0 * PORTCL - Port C Latched Register ($1005) PCL7 EQU BIT7 PCL6 EQU BIT6 PCL5 EQU BIT5 PCL4 EQU BIT4 PCL3 EQU BIT3 PCL2 EQU BIT2 PCL1 EQU BIT1 PCL0 EQU BIT0 * DDRC - Port C Data Direction Register ($1007) DDRC7 EQU BIT7 DDRC6 EQU BIT6 DDRC5 EQU BIT5 DDRC4 EQU BIT4 DDRC3 EQU BIT3 DDRC2 EQU BIT2 DDRC1 EQU BIT1 DDRC0 EQU BIT0 * PORTD - Port D Data Register ($1008) PD5 EQU BIT5 PD4 EQU BIT4 PD3 EQU BIT3 PD2 EQU BIT2 ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 5 PD1 EQU BIT1 PD0 EQU BIT0 * DDRD - Port D Data Register ($1009) DDRD5 EQU BIT5 DDRD4 EQU BIT4 DDRD3 EQU BIT3 DDRD2 EQU BIT2 DDRD1 EQU BIT1 DDRD0 EQU BIT0 * PORTE - Port E Data Register ($100a) PE7 EQU BIT7 PE6 EQU BIT6 PE5 EQU BIT5 PE4 EQU BIT4 PE3 EQU BIT3 PE2 EQU BIT2 PE1 EQU BIT1 PE0 EQU BIT0 *----------------- * Timer facility * CFORC - Timer Compare Force Register ($100b) FOC1 EQU BIT7 FOC2 EQU BIT6 FOC3 EQU BIT5 FOC4 EQU BIT4 FOC5 EQU BIT3 * OC1M - Output Compare 1 Mask Register ($100c) OC1M7 EQU BIT7 OC1M6 EQU BIT6 OC1M5 EQU BIT5 OC1M4 EQU BIT4 OC1M3 EQU BIT3 * OC1D - Output Compare 1 Data Register ($100d) OC1D7 EQU BIT7 OC1D6 EQU BIT6 OC1D5 EQU BIT5 OC1D4 EQU BIT4 OC1D3 EQU BIT3 * TCTL1 - Timer Control Register 1 ($1020) OM2 EQU BIT7 OL2 EQU BIT6 OM3 EQU BIT5 OL3 EQU BIT4 OM4 EQU BIT3 OL4 EQU BIT2 OM5 EQU BIT1 OL5 EQU BIT0 * TCTL2 - Timer Control Register 2 ($1021) EDG4B EQU BIT7 EDG4A EQU BIT6 ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 6 EDG1B EQU BIT5 EDG1A EQU BIT4 EDG2B EQU BIT3 EDG2A EQU BIT2 EDG3B EQU BIT1 EDG3A EQU BIT0 * TMSK1 - Timer Interrupt Mask 1 Register ($1022) OC1I EQU BIT7 OC2I EQU BIT6 OC3I EQU BIT5 OC4I EQU BIT4 I4O5I EQU BIT3 OC5I EQU I4O5I IC4I EQU I4O5I IC1I EQU BIT2 IC2I EQU BIT1 IC3I EQU BIT0 * TFLG1 - Timer Interrupt Flag 1 ($1023) OC1F EQU BIT7 OC2F EQU BIT6 OC3F EQU BIT5 OC4F EQU BIT4 I4O5F EQU BIT3 OC5F EQU I4O5F IC4F EQU I4O5F IC1F EQU BIT2 IC2F EQU BIT1 IC3F EQU BIT0 * TMSK2 - Timer Interrupt Mask 2 Register ($1024) TOI EQU BIT7 RTII EQU BIT6 PAOVI EQU BIT5 PAII EQU BIT4 PR1 EQU BIT1 PR0 EQU BIT0 * TFLG2 - Timer Interrupt Flag 2 ($1025) TOF EQU BIT7 RTIF EQU BIT6 PAOVF EQU BIT5 PAIF EQU BIT4 * PACTL - Pulse Accumulator Control Register ($1026) DDRA7 EQU BIT7 PAEN EQU BIT6 PAMOD EQU BIT5 PEDGE EQU BIT4 DDRA3 EQU BIT3 I4O5 EQU BIT2 RTR1 EQU BIT1 RTR0 EQU BIT0 *----------------------------------- * Serial Peripheral Interface (SPI) * SPCR - Serial Peripheral Control Register ($1028) ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 7 SPIE EQU BIT7 SPE EQU BIT6 DWOM EQU BIT5 MSTR EQU BIT4 CPOL EQU BIT3 CPHA EQU BIT2 SPR1 EQU BIT1 SPR0 EQU BIT0 * SPSR - Serial Peripheral Status Register ($1029) SPIF EQU BIT7 WCOL EQU BIT6 MODF EQU BIT4 *--------------------------------------- * Serial Communications Interface (SCI) * BAUD - Baud Rate Register ($102b) TCLR EQU BIT7 SCP2 EQU BIT6 SCP1 EQU BIT5 SCP0 EQU BIT4 RCKB EQU BIT3 SCR2 EQU BIT2 SCR1 EQU BIT1 SCR0 EQU BIT0 * SCCR1 - Serial Communications Control Register 1 ($102b) R8 EQU BIT7 T8 EQU BIT6 M EQU BIT4 WAKE EQU BIT3 * SCCR2 - Serial Communications Control Register 2 ($102c) TIE EQU BIT7 TCIE EQU BIT6 RIE EQU BIT5 ILIE EQU BIT4 TE EQU BIT3 RE EQU BIT2 RWU EQU BIT1 SBK EQU BIT0 * SCSR - Serial Communications Status Register ($102e) TDRE EQU BIT7 TC EQU BIT6 RDRF EQU BIT5 IDLE EQU BIT4 OR EQU BIT3 NF EQU BIT2 FE EQU BIT1 * SCDR - Serial Communications Data Register ($102f) R7T7 EQU BIT7 R6T6 EQU BIT6 R5T5 EQU BIT5 R4T4 EQU BIT4 R3T3 EQU BIT3 R2T2 EQU BIT2 ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 8 R1T1 EQU BIT1 R0T0 EQU BIT0 *----------------------------------- * Analog-to-Digital (A2D) Converter * ADCTL - Analog-to-Digital Control Status Register ($1030) CCF EQU BIT7 SCAN EQU BIT5 MULT EQU BIT4 CD EQU BIT3 CC EQU BIT2 CB EQU BIT1 CA EQU BIT0 * BPROT - Block Protect Register ($1035) PTCON EQU BIT4 BPRT3 EQU BIT3 BPRT2 EQU BIT2 BPRT1 EQU BIT1 BRPT0 EQU BIT0 * EPROG - EPROM Programming Control Register ($1036) MBE EQU BIT7 ELAT EQU BIT6 EXCOL EQU BIT5 EXROW EQU BIT4 T1 EQU BIT2 T0 EQU BIT1 PGM EQU BIT0 * OPTION - System Configuration Options Register ($1039) ADPU EQU BIT7 CSEL EQU BIT6 IRQE EQU BIT5 DLY EQU BIT4 CME EQU BIT3 CR1 EQU BIT1 CR0 EQU BIT0 * PPROG - EPROM and EEPROM Programming Control Register . ($103b) ODD EQU BIT7 EVEN EQU BIT6 BYTE EQU BIT4 ROW EQU BIT3 ERASE EQU BIT2 EELAT EQU BIT1 EPGM EQU BIT0 * HPRIO - Highest Priority I Bit Interrupt and Miscellaneous . Register ($103c) RBOOT EQU BIT7 SMOD EQU BIT6 MDA EQU BIT5 IRVNE EQU BIT4 PSEL3 EQU BIT3 PSEL2 EQU BIT2 PSEL1 EQU BIT1 ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 9 PSEL0 EQU BIT0 * INIT - RAM and I/O Mapping Register ($103d) RAM3 EQU BIT7 RAM2 EQU BIT6 RAM1 EQU BIT5 RAM0 EQU BIT4 REG3 EQU BIT3 REG2 EQU BIT2 REG1 EQU BIT1 REG0 EQU BIT0 * CONFIG - System Configuration Register ($103f) NOSEC EQU BIT3 NOCOP EQU BIT2 ROMON EQU BIT1 EEON EQU BIT0 #include "registers.asm" #include "buffalo.asm" * Buffalo subroutine jumptable addresses * Each location in the jump table contains an appropriate JMP . instruction. * To use, just JSR to the jump table address that you want to . use. Buffalo_utljmp_base org $ffa0 UPCASE rmb JUMPSIZE ; Convert character to . uppercase WCHEK rmb JUMPSIZE ; Test character for . whitespace DCHEK rmb JUMPSIZE ; Check character for . delimiter INITDEV rmb JUMPSIZE ; Initialize I/O device INPUT rmb JUMPSIZE ; Read I/O device OUTPUT rmb JUMPSIZE ; Write I/O device OUTLHLF rmb JUMPSIZE ; Convert left nibble to . ASCII and output OUTRHLF rmb JUMPSIZE ; Convert right nibble to . ASCII and output OUTA rmb JUMPSIZE ; Output ASCII character OUT1BYT rmb JUMPSIZE ; Convert binary byte to 2 . ASCII characters and output OUT1BSP rmb JUMPSIZE ; Convert binary byte to 2 . ASCII characters and output followed by space OUT2BSP rmb JUMPSIZE ; Convert 2 consecutive . binary bytes to 4 ASCII characters and output followed by . space OUTCRLF rmb JUMPSIZE ; Output ASCII carriage . return followed by line feed OUTSTRG rmb JUMPSIZE ; Output ASCII string until . end of transmission ($04) OUTSTRG0 rmb JUMPSIZE ; Same as OUTSTRG except . leading carriage return and line feed is skipped INCHAR rmb JUMPSIZE ; Input ASCII character and . echo back VECINIT rmb JUMPSIZE ; Initialize RAM interrupt . vector table * Buffalo interrupt vector jumptable addresses ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 10 * Each location in the jump table contains an appropriate JMP . instruction. * To use, store the address of your ISR at the jumptable . address+1. Buffalo_intjmp_base org $00c4 JSCI rmb JUMPSIZE ; Serial Communications . Interface JSPI rmb JUMPSIZE ; Serial Peripheral Interface JPAIE rmb JUMPSIZE ; Pulse Accumulator input . edge JPAO rmb JUMPSIZE ; Pulse Accumulator overflow JTOF rmb JUMPSIZE ; Timer overflow JTI4C5 rmb JUMPSIZE ; Timer input capture 4 / . output compare 5 JTOC4 rmb JUMPSIZE ; Timer output compare 4 JTOC3 rmb JUMPSIZE ; Timer output compare 3 JTOC2 rmb JUMPSIZE ; Timer output compare 2 JTOC1 rmb JUMPSIZE ; Timer output compare 1 JTIC3 rmb JUMPSIZE ; Timer input capture 3 JTIC2 rmb JUMPSIZE ; Timer input capture 2 JTIC1 rmb JUMPSIZE ; Timer input capture 1 JRTI rmb JUMPSIZE ; Real-time interrupt JIRQ rmb JUMPSIZE ; IRQ pin (maskable) JXIRQ rmb JUMPSIZE ; XIRQ pin (nonmaskable) JSWI rmb JUMPSIZE ; Software Interrupt JILLOP rmb JUMPSIZE ; Illegal opcode trap JCOP rmb JUMPSIZE ; Computer Operating Properly . watchdog failure JCLM rmb JUMPSIZE ; Clock monitor failure * Pseudo-vector addresses in RAM, within the above jumptable . entries. * The +1's are to skip over the JMP instruction opcode. PVSCI equ JSCI+1 ; Serial Communications . Interface PVSPI equ JSPI+1 ; Serial Peripheral Interface PVPAIE equ JPAIE+1 ; Pulse Accumulator input . edge PVPAO equ JPAO+1 ; Pulse Accumulator overflow PVTOF equ JTOF+1 ; Timer overflow PVTI4C5 equ JTI4C5+1 ; Timer input capture 4 / . output compare 5 PVTOC4 equ JTOC4+1 ; Timer output compare 4 PVTOC3 equ JTOC3+1 ; Timer output compare 3 PVTOC2 equ JTOC2+1 ; Timer output compare 2 PVTOC1 equ JTOC1+1 ; Timer output compare 1 PVTIC3 equ JTIC3+1 ; Timer input capture 3 PVTIC2 equ JTIC2+1 ; Timer input capture 2 PVTIC1 equ JTIC1+1 ; Timer input capture 1 PVRTI equ JRTI+1 ; Real-time interrupt PVIRQ equ JIRQ+1 ; IRQ pin (maskable) PVXIRQ equ JXIRQ+1 ; XIRQ pin (nonmaskable) PVSWI equ JSWI+1 ; Software Interrupt PVILLOP equ JILLOP+1 ; Illegal opcode trap PVCOP equ JCOP+1 ; Computer Operating Properly . watchdog failure PVCLM equ JCLM+1 ; Clock monitor failure #include "buffalo.asm" org $2000 2000 7E 23 BB jmp main ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 11 #include "lcd.asm" *#include "keypad.asm" #include "timer.asm" *#include "buffalo.asm" ; For SCI routines OUTSTRG0 and . OUTCRLF * Print debug message pointed to by X printmsg: 215F BD FF CA jsr OUTSTRG0 2162 BD FF C4 jsr OUTCRLF 2165 39 rts mycrlf: 2166 36 psha 2167 86 0D LDAA #CR 2169 BD FF AF JSR OUTPUT 216C 86 0A LDAA #LF 216E BD FF AF JSR OUTPUT 2171 32 pula 2172 39 RTS * Print current values of all registers. printregs: 2173 36 psha ; Store all registers 2174 07 tpa 2175 B7 22 64 staa ccr 2178 32 pula 2179 B7 22 5A staa accA 217C F7 22 5B stab accB 217F FD 22 5C std accD 2182 FF 22 5E stx regIX 2185 18 FF 22 60 sty regIY 2189 3C pshx 218A 36 psha 218B CE 22 65 ldx #aeq 218E BD FF C7 jsr outstrg 2191 CE 22 5A ldx #accA 2194 BD FF BE jsr out1bsp 2197 CE 22 68 ldx #beq 219A BD FF CA jsr outstrg0 219D CE 22 5B ldx #accB 21A0 BD FF BE jsr out1bsp 21A3 CE 22 6B ldx #deq 21A6 BD FF CA jsr outstrg0 21A9 CE 22 5C ldx #accD 21AC BD FF C1 jsr out2bsp 21AF CE 22 6E ldx #xeq 21B2 BD FF CA jsr outstrg0 21B5 CE 22 5E ldx #regIX 21B8 BD FF C1 jsr out2bsp 21BB CE 22 71 ldx #yeq 21BE BD FF CA jsr outstrg0 21C1 CE 22 60 ldx #regIY 21C4 BD FF C1 jsr out2bsp 21C7 CE 22 74 ldx #ccreq 21CA BD FF CA jsr outstrg0 21CD CE 22 64 ldx #ccr 21D0 BD FF BE jsr out1bsp 21D3 BD FF C4 jsr outcrlf 21D6 B6 22 64 ldaa ccr 21D9 06 tap 21DA 32 pula 21DB 38 pulx ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 12 21DC 39 rts * Print current value of A accumulator. 21DD B7 22 5A printA: staa accA 21E0 36 psha 21E1 3C pshx 21E2 CE 22 5A ldx #accA 21E5 BD FF BE jsr out1bsp 21E8 38 pulx 21E9 32 pula 21EA 39 rts 21EB F7 22 5B printB: stab accB 21EE 36 psha 21EF 3C pshx 21F0 CE 22 5B ldx #accB 21F3 BD FF BE jsr out1bsp 21F6 38 pulx 21F7 32 pula 21F8 39 rts 21F9 FD 22 5C printD: std accD 21FC 36 psha 21FD 3C pshx 21FE CE 22 5C ldx #accD 2201 BD FF C1 jsr out2bsp 2204 38 pulx 2205 32 pula 2206 39 rts 2207 FF 22 5E printX: stx regIX 220A 36 psha 220B 3C pshx 220C CE 22 5E ldx #regIX 220F BD FF C1 jsr out2bsp 2212 38 pulx 2213 32 pula 2214 39 rts 2215 18 FF 22 60 printY: sty regIY 2219 36 psha 221A 3C pshx 221B CE 22 60 ldx #regIY 221E BD FF C1 jsr out2bsp 2221 38 pulx 2222 32 pula 2223 18 FE 22 60 ldy regIY 2227 39 rts 2228 18 FF 22 60 printS: sty regIY 222C 18 30 tsy 222E 18 08 iny 2230 18 FF 22 62 sty regSP 2234 18 FE 22 60 ldy regIY 2238 36 psha 2239 3C pshx 223A 18 3C pshy 223C CE 22 62 ldx #regSP 223F BD FF C1 jsr out2bsp 2242 18 38 puly 2244 38 pulx 2245 32 pula 2246 39 rts ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 13 printCCR: 2247 36 psha 2248 07 tpa 2249 B7 22 64 staa ccr 224C 3C pshx 224D CE 22 64 ldx #ccr 2250 BD FF BE jsr out1bsp 2253 38 pulx 2254 B6 22 64 ldaa ccr 2257 06 tap 2258 32 pula 2259 39 rts accA: rmb 1 accB: rmb 1 accD: rmb 2 regIX: rmb 2 regIY: rmb 2 regSP: rmb 2 ccr: rmb 1 2265 41 3D aeq: fcc "A=" 2267 04 fcb EOT 2268 42 3D beq: fcc "B=" 226A 04 fcb EOT 226B 44 3D deq: fcc "D=" 226D 04 fcb EOT 226E 58 3D xeq: fcc "X=" 2270 04 fcb EOT 2271 59 3D yeq: fcc "Y=" 2273 04 fcb EOT 2274 43 43 52 3D ccreq: fcc "CCR=" 2278 04 fcb EOT * Wait for user to hit enter 2279 36 pause: psha 227A BD FF CD jsr inchar 227D 32 pula 227E 39 rts #include "debug.asm" *------------------------------------------------------------ . --------------------------------------- * Subroutine: setup_periodic_alarm * Purpose: * Arrange for an alarm to go off at regular intervals, . and call a specific subroutine every * time it does. Uses the HC11's built-in Timer Output . Compare facility. Supports up to 5 * independent alarms. User is responsible for doing . the CLI to enable interrupts (either * before or after calling this subroutine). * Inputs: * A = Alarm number, 0-4 * X = Pointer to subroutine to invoke (not an ISR). * Y = Alarm period in timer cycles, 0-65535. * Side effects: * Timer output compare TOC(A+1) is set up to call . subroutine at X. * All registers are trashed. *------------------------------------------------------------ . --------------------------------------- * First, declare frame pointer offsets for local variables: ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 14 lOffset: equ 0 ; For offsets . calculated from alarm numbers. lPseudo: equ lOffset+2 ; For pointer to . pseudo-vector address. lCCR: equ lPseudo+2 ; For preserving . caller's condition code register. lPeriod: equ lCCR+1 ; For preserving . caller's Y / period of alarm. lSub: equ lPeriod+2 ; For preserving . caller's X / pointer to user subroutine. lAlarm: equ lSub+2 ; For preserving . caller's A / alarm number. sLocals: equ lAlarm+1 ; Total space . occupied by local variables. * Error messages. 227F 41 6C 61 72 alarm_too_big: fcc "Alarm number is too big." . 2283 6D 20 6E 75 . 2287 6D 6D 65 72 . 228B 20 69 73 20 . 228F 74 6F 6F 00 . 2293 62 69 67 2E 2297 04 fcb EOT * The actual subroutine starts here. setup_periodic_alarm: * Save arguments, reserve space for local variables, and set . up frame pointer. 2298 36 psha ; Stack variable lAlarm <- . alarm number A. 2299 3C pshx ; Stack variable lSub <- . subroutine pointer X. 229A 18 3C pshy ; Stack variable lPeriod <- . alarm period Y. 229C 07 tpa ; Copy caller's predicate . bits (CCR) to A. 229D 36 psha ; Stack variable lCCR <- . caller's predicates. 229E 18 30 tsy ; Let Y point to top of stack . (lCCR). 22A0 18 8F xgdy ; Put frame pointer Y into D. 22A2 83 00 04 subd #lCCR ; Adjust it to make space for . additional locals above lCCR. (lOffset, lPseudo) 22A5 18 8F xgdy ; Put frame pointer back into . Y. 22A7 18 35 tys ; Move stack pointer above . locals frame, in case we want to call subroutines. * Do some error checking on our input arguments. 22A9 18 A6 09 ldaa lAlarm,y ; A = Alarm number. 22AC 81 04 cmpa #4 ; Max possible alarm number. 22AE 23 09 bls spa4 ; If that or lower, we're OK. 22B0 CE 22 7F ldx #alarm_too_big ; Select error message: Alarm . is too big. 22B3 BD FF C7 jsr outstrg ; Print error message to SCI. 22B6 7E 23 27 jmp spa3 ; Exit from subroutine . without really doing anything. spa4: * Disable interrupts before we start changing anything. 22B9 0F sei ; Mask interrupts while we're . rearranging things. ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 15 * First, we calculate the pseudo-vector address in Buffalo's . jumptable that we'll need to set. 22BA 18 A6 09 ldaa lAlarm,y ; A = Alarm number. 22BD C6 03 ldab #JUMPSIZE ; B = Size of a jump . instruction. 22BF 3D mul ; D = Offset to the jumptable . entry we want 22C0 18 ED 00 std lOffset,y ; Store it in lOffset local . variable. 22C3 CC 00 E0 ldd #PVTOC1 ; Point D at last TOC . jumptable pseudo-vector entry. 22C6 18 A3 00 subd lOffset,y ; Subtract the lOffset we . saved earlier. 22C9 18 ED 02 std lPseudo,y ; Store D in lPseudo local . variable. * Next, find the address of the appropriate ISR. 22CC 18 E6 09 ldab lAlarm,y ; Load alarm number. 22CF 58 lslb ; Double to get a word . offset. 22D0 4F clra ; Clear MSB of D; effectively . transfers B->D. 22D1 18 ED 00 std lOffset,y ; Store in lOffset local . variable. 22D4 C3 23 99 addd #TOC_ISRs ; Add base address of TOC ISR . table. 22D7 8F xgdx ; Transfer TOC ISR table . entry pointer to X. 22D8 EC 00 ldd 0,x ; Transfer TOC ISR pointer to . D. * Now, store the ISR address in the pseudo-vector location. 22DA CD EE 02 ldx lPseudo,y ; Load pseudo-vector pointer . we computed in previous section. 22DD ED 00 std 0,x ; Store TOC ISR pointer at . pseudo-vector location. This sets up the vector. * Figure out where to store our subroutine pointer. 22DF 18 EC 00 ldd lOffset,y ; Load offset we computed . earlier. 22E2 C3 23 AD addd #sub1 ; Add base of subroutine . pointer table. 22E5 8F xgdx ; X now points to subroutine . pointer table entry. * Store the subroutine pointer there. 22E6 18 EC 07 ldd lSub,y ; Load pointer to the actual . subroutine into D. 22E9 ED 00 std 0,x ; Store it in the subroutine . pointer table entry. * Now, compute the appropriate mask bit to select OCa in the . TMSK1 and TFLG1 registers. 22EB C6 80 ldab #OC1I ; Bit mask for OC1I register . bit. (Also is OC1F.) 22ED 18 A6 09 ldaa lAlarm,y ; This is the alarm number 0- . 4 we pushed earlier. 22F0 27 04 spa0: beq spa1 ; If it's 0, the mask we have . now is the right one. 22F2 54 lsrb ; Shift the mask right one . position (go to next OC) 22F3 4A deca ; Subtract 1 from alarm . number. 22F4 20 FA bra spa0 ; Keep looping. ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 16 spa1: * The following code actually enables the interrupts on . Output Compare #a to occur. 22F6 F7 10 23 stab TFLG1 ; Storing "1" turns OFF bit . OCaF in TFLG1 (clears state of OCaF flag). 22F9 FA 10 22 orab TMSK1 ; This prevents the next line . from turning off other OCxI bits. 22FC F7 10 22 stab TMSK1 ; Turns on bit OCaI in TMSK1 . (enables interrupt OCaI). * Remember the period, for use by the ISR. 22FF 18 EC 00 ldd lOffset,y ; Load offset computer . earlier. 2302 C3 23 A3 addd #per1 ; Add to base of table of . periods. 2305 8F xgdx ; Point X at the entry we . want. 2306 18 EC 05 ldd lPeriod,y ; Load the period. 2309 ED 00 std 0,x ; Store X in the table of . periods. * Finally, we set the initial OCa alarm time relative to the . present time. 230B 18 EC 00 ldd lOffset,y ; Load offset which we . computed earlier. 230E F3 10 16 addd TOC1 ; Add to base of TOC . registers to point to TOCa. 2311 8F xgdx ; Put the pointer into regIX. 2312 FC 10 0E ldd TCNT ; Load the present system . timer value. 2315 18 E3 05 addd lPeriod,y ; Add it to the alarm period . that we saved earlier. 2318 ED 00 std 0,x ; Store it in the appropriate . TOCa register. (This line sets the initial alarm trigger . time.) * Finally, if alarm 4 (OC5) was selected, we have to . configure pin PA3 as OC5 rather than IC4. 231A 18 A6 09 ldaa lAlarm,y ; Load A with the alarm . number. 231D 81 04 cmpa #4 ; Was it alarm #4? . (Representing OC5.) 231F 26 06 bne spa2 ; If not, then don't... 2321 CE 10 26 ldx #PACTL ; Select PACTL . register. 2324 1D 00 04 bclr 0,x I4O5 ; Clear the I4/O5 bit . (select OC5 rather than IC4 for pin PA3). spa2: * Throw away all the locals, restore stack pointer and the I . bit. Don't bother restoring any other registers. 2327 18 A6 04 spa3: ldaa lCCR,y ; Load caller's CCR (really . we just care about I). 232A 06 tap ; Transfer it to the real . CCR. (This may re-enable interrupts, if they were enabled in . caller.) 232B 18 8F xgdy ; Move frame pointer into D. 232D C3 00 0A addd #sLocals ; Bump it up past all the . locals. (Including pushed registers.) 2330 18 8F xgdy ; Transfer it back to Y. 2332 18 35 tys ; And from there back to the . stack pointer. Now it's safe to return. 2334 39 rts ; Return from setup_periodic_ . alarm subroutine. ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 17 *------------------------------------------------------------ . ------------ * Interrupt Service Routines that may be set up by setup_ . periodic_alarm. *------------------------------------------------------------ . ------------ ISR_TOC1: 2335 FC 10 16 ldd TOC1 ; Get current TOC1 alarm time. 2338 F3 23 A3 addd per1 ; Add the period for this periodic . timer. 233B FD 10 16 std TOC1 ; Store it as the new alarm time. 233E FE 23 AD ldx sub1 ; Load first subroutine address. 2341 AD 00 jsr 0,x ; Jump to that subroutine. 2343 86 80 ldaa #OC1F ; Select OC1F flag (in TFLG1 . register). 2345 B7 10 23 staa TFLG1 ; Write 1 to OC1F in TFLG1 to turn . off OC1F, which resets TOC1. 2348 3B rti ; Return from ISR_TOC1. ISR_TOC2: 2349 FC 10 18 ldd TOC2 ; Get current TOC2 alarm time. 234C F3 23 A5 addd per2 ; Add the period for this periodic . timer. 234F FD 10 18 std TOC2 ; Store it as the new alarm time. 2352 FE 23 AF ldx sub2 ; Load 2nd subroutine address. 2355 AD 00 jsr 0,x ; Jump to that subroutine. 2357 86 40 ldaa #OC2F ; Select OC2F flag (in TFLG1 . register). 2359 B7 10 23 staa TFLG1 ; Write 1 to OC2F in TFLG1 to turn . off OC2F, which resets TOC2. 235C 3B rti ; Return from ISR_TOC2. ISR_TOC3: 235D FC 10 1A ldd TOC3 ; Get current TOC3 alarm time. 2360 F3 23 A7 addd per3 ; Add the period for this periodic . timer. 2363 FD 10 1A std TOC3 ; Store it as the new alarm time. 2366 FE 23 B1 ldx sub3 ; Load 3rd subroutine address. 2369 AD 00 jsr 0,x ; Jump to that subroutine. 236B 86 20 ldaa #OC3F ; Select OC3F flag (in TFLG1 . register). 236D B7 10 23 staa TFLG1 ; Write 1 to OC3F in TFLG1 to turn . off OC3F, which resets TOC3. 2370 3B rti ; Return from ISR_TOC3. ISR_TOC4: 2371 FC 10 1C ldd TOC4 ; Get current TOC4 alarm time. 2374 F3 23 A9 addd per4 ; Add the period for this periodic . timer. 2377 FD 10 1C std TOC4 ; Store it as the new alarm time. 237A FE 23 B3 ldx sub4 ; Load 4th subroutine address. 237D AD 00 jsr 0,x ; Jump to that subroutine. 237F 86 10 ldaa #OC4F ; Select OC4F flag (in TFLG1 . register). 2381 B7 10 23 staa TFLG1 ; Write 1 to OC4F in TFLG1 to turn . off OC4F, which resets TOC4. 2384 3B rti ; Return from ISR_TOC3. ISR_TOC5: 2385 FC 10 1E ldd TOC5 ; Get current TOC5 alarm time. 2388 F3 23 AB addd per5 ; Add the period for this periodic . timer. 238B FD 10 1E std TOC5 ; Store it as the new alarm time. 238E FE 23 B5 ldx sub5 ; Load 5th subroutine address. ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 18 2391 AD 00 jsr 0,x ; Jump to that subroutine. 2393 86 08 ldaa #OC5F ; Select OC5F flag (in TFLG1 . register). 2395 B7 10 23 staa TFLG1 ; Write 1 to OC5F in TFLG1 to turn . off OC5F, which resets TOC5. 2398 3B rti ; Return from ISR_TOC5. *------------------------------------------------------ * Persistent variables needed by setup_periodic_alarm. *------------------------------------------------------ * Table of pointers to all of our ISRs for the TOC . interrupts. TOC_ISRs: 2399 23 35 fdb ISR_TOC1 239B 23 49 fdb ISR_TOC2 239D 23 5D fdb ISR_TOC3 239F 23 71 fdb ISR_TOC4 23A1 23 85 fdb ISR_TOC5 * Programmers: Be sure to locate the below variable data . region in RAM. * Data region for remembering the periods for the 5 possible . periodic alarms. per1: rmb WORDSIZE per2: rmb WORDSIZE per3: rmb WORDSIZE per4: rmb WORDSIZE per5: rmb WORDSIZE * Data region for remembering the addresses of the . subroutines to call upon alarm. sub1: rmb WORDSIZE sub2: rmb WORDSIZE sub3: rmb WORDSIZE sub4: rmb WORDSIZE sub5: rmb WORDSIZE #include "timer.asm" glyph_table equ 0 ; No glyph table xcoord: rmb 1 ycoord: rmb 1 mydel: rmb 2 main: 23BB BD 20 03 jsr init_LCD 23BE 86 0C ldaa #DISP_ONOFF|D_DISP ; No blink/cursor 23C0 BD 21 05 jsr send_cmd * jsr init_keypad 23C3 86 00 ldaa #0 23C5 C6 00 ldab #0 23C7 B7 23 B7 staa xcoord 23CA F7 23 B8 stab ycoord 23CD 86 41 ldaa #'A 23CF BD 21 0C jsr write_lcd 23D2 CE FF FF ldx #$ffff 23D5 FF 23 B9 stx mydel 23D8 86 00 ldaa #0 ; Select alarm #0 ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 19 . (really this means OC1). 23DA CE 24 0D ldx #mysub ; Select subroutine . "mysub" (below). 23DD 18 FE 23 B9 ldy mydel ; Select my delay . value. 23E1 BD 22 98 jsr setup_periodic_alarm ; Call mysub every . mydel timer ticks. 23E4 0E cli ; Enable interrupts 23E5 CE 23 F5 ldx #msg2 23E8 BD FF C7 jsr outstrg inf: 23EB 3E wai * ldx #0 * jsr dloop * ldx #msg2 * jsr outstrg 23EC 20 FD bra inf 23EE 69 6E 20 49 msg1: fcc "in ISR" . 23F2 53 52 23F4 04 fcb EOT 23F5 57 61 69 74 msg2: fcc "Waiting for interrupt." . 23F9 69 6E 67 20 . 23FD 66 6F 72 20 . 2401 69 6E 74 65 . 2405 72 72 75 70 . 2409 74 2E 240B 04 fcb EOT 240C 05 mycount: fcb 5 240D 7A 24 0C mysub: dec mycount 2410 26 3E bne return 2412 86 05 ldaa #5 2414 B7 24 0C staa mycount * ldx #msg1 * jsr outstrg 2417 B6 23 B7 ldaa xcoord 241A F6 23 B8 ldab ycoord 241D BD 20 90 jsr gotoxy 2420 86 20 ldaa #SPACE 2422 BD 21 0C jsr write_lcd 2425 F6 23 B8 ldab ycoord 2428 5C incb 2429 C1 04 cmpb #4 242B 26 12 bne yok 242D C6 00 ldab #0 242F F7 23 B8 stab ycoord 2432 B6 23 B7 ldaa xcoord 2435 4C inca 2436 81 14 cmpa #20 2438 26 02 bne xok 243A 86 00 ldaa #0 243C B7 23 B7 xok: staa xcoord * jsr adjust_delay 243F F7 23 B8 yok: stab ycoord 2442 B6 23 B7 ldaa xcoord 2445 F6 23 B8 ldab ycoord 2448 BD 20 90 jsr gotoxy ADDR B1 B2 B3 B4 F:\chicken\timertest2.asm PAGE 20 244B 86 41 ldaa #'A 244D BD 21 0C jsr write_lcd 2450 39 return: rts adjust_delay: 2451 FC 23 B9 ldd mydel 2454 44 lsra ; shift D right 2455 56 rorb 2456 FD 23 B9 std mydel 2459 CE 23 B9 ldx #mydel 245C BD FF C1 jsr out2bsp 245F BD FF C4 jsr outcrlf 2462 39 rts Symbol Table ALL1S 00FF CLR_HOM 0001 CA 0001 ETB 0017 SEND_CMD 2105 CB 0002 MULT 0010 CC 0004 CD 0008 NOCOP 0004 CR 000D STORE_GLYPH 2137 INCHAR FFCD EDG1A 0010 ETX 0003 EDG1B 0020 RL_RIGHT 0004 BPRT1 0002 BPRT2 0004 BPRT3 0008 ID_INC 0002 STAF 0080 ENDSTR 00FF OPTION 1039 STAI 0040 US 001F ROW4_END 0067 CONFIG 103F TMPX 208F PORTCL 1005 FOC1 0080 FOC2 0040 OUTA FFB8 FOC3 0020 PLS 0004 FOC4 0010 BRPT0 0001 FOC5 0008 PVTOC1 00E0 PVTOC2 00DD PVTOC3 00DA PAMOD 0020 PVTOC4 00D7 EDG2A 0004 EDG2B 0008 B_BLINK 0001 YOK 243F PVCOP 00FB Symbol Table F:\chicken\timertest2.asm PAGE 21 ROW1_START 0000 DDRAM_ADDRSET 0080 WRITE_LCD 210C VT 000B CPOL 0008 EM 0019 PEDGE 0010 PAOVF 0020 ALARM_TOO_BIG 227F NOMORE 20EB PAOVI 0020 TIE 0080 EDG3A 0001 EVEN 0040 IDLE 0010 EDG3B 0002 EXROW 0010 PER1 23A3 PER2 23A5 PVRTI 00EC PER3 23A7 FE 0002 PER4 23A9 FF 000C RTIF 0040 PER5 23AB M 0010 PVTIC1 00E9 PVTIC2 00E6 RTII 0040 PCL0 0001 PVTIC3 00E3 PCL1 0002 I4O5 0004 PCL2 0004 COPRST 103A TI4O5H 101E SOH 0001 R6T6 0040 PCL3 0008 PCL4 0010 MYCRLF 2166 CR0 0001 PCL5 0020 CR1 0002 PCL6 0040 TI4O5L 101F BEL 0007 PCL7 0080 PVIRQ 00EF JCLM 00FD FS 001C ROW3_END 0027 BEQ 2268 PACTL 1026 REG0 0001 PAEN 0040 EDG4A 0040 REG1 0002 EDG4B 0080 INIT 103D DLE 0010 REG2 0004 REG3 0008 R3T3 0008 Symbol Table F:\chicken\timertest2.asm PAGE 22 ROW_LENGTH 0014 TCTL1 1020 DLOOP 211D TCTL2 1021 XEQ 226E SPIE 0080 SPIF 0080 SPE 0040 LSTRL 20D7 EGA 0002 WAIT_LCD 2113 TI4O5 101E LCD_OUT 20A9 PVSPI 00C8 R0T0 0001 GS 001D TDRE 0080 OUTLHLF FFB2 SFLAG 0080 TMSK1 1022 ZFLAG 0004 JUMPSIZE 0003 ODD 0080 DLY 0010 TMSK2 1024 SHOW_GLYPHS 2155 SETUP_PERIODIC_ALARM2298 SPACE 0020 STORE_GLYPHS 2121 N_2LINES 0008 RAM0 0010 RAM1 0020 BIT10 0004 RAM2 0040 SCCR1 102C BIT11 0008 UPCASE FFA0 RAM3 0080 SCCR2 102D BIT12 0010 CAN 0018 BIT13 0020 IC1F 0004 BIT14 0040 MYDEL 23B9 BIT15 0080 IC1I 0004 NEXTGL 2125 EEON 0001 OC1D3 0008 OUTRHLF FFB5 OC1D4 0010 PIOC 1002 MYCOUNT 240C OC1D5 0020 OC1D6 0040 OC1D7 0080 BAUD 102B DCHEK FFA6 NEXTROW 2145 LCD_CTL B5F0 OC1D 100D PR0 0001 SLOCALS 000A JTOC1 00DF Symbol Table F:\chicken\timertest2.asm PAGE 23 PR1 0002 OC1F 0080 JTOC2 00DC EXCOL 0020 INIT_LCD 2003 ROW2_END 0053 ENT_MOD 0004 JTOC3 00D9 LCD_BASE B5F0 JTOC4 00D6 IC2F 0002 OC1I 0080 EPGM 0001 RWU 0002 IC2I 0002 TIC1H 1010 OC1M 100C SC_SHIFT 0008 CWOM 0020 PA0 0001 PA1 0002 ADCTL 1030 TIC1L 1011 GLYPH_TABLE 0000 PA2 0004 PA3 0008 PA4 0010 SUB1 23AD DL_8BIT 0010 PA5 0020 SUB2 23AF LCCR 0004 JCOP 00FA VECINIT FFD0 OUTCRLF FFC4 PA6 0040 SUB3 23B1 PA7 0080 SUB4 23B3 BUFFALO_INTJMP_BASE00C4 CCF 0080 SUB5 23B5 EPROG 1036 OC2F 0040 IC3F 0001 OC2I 0040 TOC1H 1016 SHIFT_LEFT 20FE TFLG1 1023 TFLG2 1025 CCR 2264 IC3I 0001 TIC2H 1012 MAIN 23BB TOC1L 1017 PTCON 0010 PAIF 0010 PB0 0001 TCIE 0040 PB1 0002 TIC2L 1013 JTIC1 00E8 PB2 0004 JTIC2 00E5 PAII 0010 Symbol Table F:\chicken\timertest2.asm PAGE 24 PB3 0008 JTIC3 00E2 SCP0 0010 PB4 0010 SCP1 0020 PB5 0020 JRTI 00EB SCP2 0040 PB6 0040 PB7 0080 SBK 0001 PVPAO 00CE OC3F 0020 CFORC 100B IC4F 0008 OC3I 0020 TOC2H 1018 JIRQ 00EE PSEL0 0001 PSEL1 0002 IC4I 0008 TIC3H 1014 PSEL2 0004 TOC2L 1019 PSEL3 0008 LSUB 0007 PRINTREGS 2173 PC0 0001 PVXIRQ 00F2 PC1 0002 TIC3L 1015 PC2 0004 PC3 0008 ROW1_END 0013 PC4 0010 PC5 0020 PC6 0040 PC7 0080 TOF 0080 NOSEC 0008 R7T7 0080 TOI 0080 PRINTCCR 2247 PVTOF 00D1 PVSCI 00C5 STX 0002 CSEL 0040 SUB 001A LF 000A RIE 0020 OC4F 0010 MBE 0080 REGSP 2262 OC4I 0010 TOC3H 101A JSPI 00C7 ROW4_START 0054 F_5X10DOTS 0004 TOC3L 101B CFLAG 0001 PD0 0001 ISR_TOC1 2335 ILIE 0010 PD1 0002 ISR_TOC2 2349 Symbol Table F:\chicken\timertest2.asm PAGE 25 R4T4 0010 PD2 0004 ISR_TOC3 235D PD3 0008 ISR_TOC4 2371 LOFFSET 0000 SCR0 0001 PD4 0010 ISR_TOC5 2385 YEQ 2271 OUT1BSP FFBE SCR1 0002 PD5 0020 XFLAG 0040 SCR2 0004 RBASE 1000 YCOORD 23B8 OC5F 0008 S_SHIFT 0001 R1T1 0002 DDRA3 0008 ACCA 225A RDRF 0020 MODF 0010 OC5I 0008 OIN 0008 TOC4H 101C ACCB 225B HNDS 0010 ACCD 225C LCD_DAT B5F1 DDRA7 0080 TOC4L 101D PRINTMSG 215F PE0 0001 PRINTA 21DD PE1 0002 PRINTB 21EB PE2 0004 PE3 0008 PRINTD 21F9 PE4 0010 PE5 0020 TOC_ISRS 2399 PE6 0040 PE7 0080 SMOD 0040 ROMON 0002 MDA 0020 JTI4C5 00D3 JILLOP 00F7 NF 0004 TCLR 0080 WCHEK FFA3 RTR0 0001 WORDSIZE 0002 RTR1 0002 HPRIO 103C PRINTS 2228 SCAN 0020 PVPAIE 00CB DC1 0011 PRINTX 2207 DC2 0012 LPSEUDO 0002 Symbol Table F:\chicken\timertest2.asm PAGE 26 PRINTY 2215 DC3 0013 D_DISP 0004 PVSWI 00F5 DC4 0014 OUTSTRG0 FFCA WAIT_LOOP 2117 RET_HOM 0002 LOCMAP 203F CCREQ 2274 ENQ 0005 OL2 0040 IFLAG 0010 OL3 0010 DDRC0 0001 TAB 0009 OL4 0004 DDRC1 0002 OL5 0001 DDRC2 0004 SCSR 102E DDRC3 0008 LCD_FIX 20CE ADPU 0080 DDRC4 0010 SPR0 0001 DDRC5 0020 SPR1 0002 CPHA 0004 DDRC6 0040 DDRC7 0080 DISP_ONOFF 0008 DWOM 0020 LCD_AD1 20C0 LCD_AD2 20C4 IRVNE 0010 OR 0008 LCD_AD3 20C8 ADR1 1031 SPA0 22F0 LCD_AD4 20CC ADR2 1032 SPA1 22F6 ROW3_START 0014 JPAO 00CD BUFFALO_UTLJMP_BASEFFA0 ADR3 1033 SPA2 2327 SET_LOC 20EE ADR4 1034 SPA3 2327 SPA4 22B9 JXIRQ 00F1 LCDSTR 20D5 OM2 0080 OM3 0020 DDRD0 0001 OM4 0008 DDRD1 0002 EOT 0004 OM5 0002 DDRD2 0004 CD_SHIFT 0010 DDRD3 0008 TCNT 100E Symbol Table F:\chicken\timertest2.asm PAGE 27 ELAT 0040 DDRD4 0010 DDRD5 0020 PORTA 1000 PORTB 1004 ACK 0006 PORTC 1003 PORTD 1008 PORTE 100A BIT0 0001 BIT1 0002 SYN 0016 BIT2 0004 BIT3 0008 BIT4 0010 JTOF 00D0 JSCI 00C4 PGM 0001 BIT5 0020 BIT6 0040 BIT7 0080 XOK 243C DDRC 1007 BIT8 0001 DDRD 1009 BIT9 0002 NAK 0015 I4O5F 0008 MSTR 0010 I4O5I 0008 WCOL 0040 GOTOXY 2090 RETURN 2450 PRINTIT 2156 R8 0080 PPROG 103B HFLAG 0020 OC1M3 0008 TCNTH 100E OC1M4 0010 SCDR 102F PVTI4C5 00D4 OUTSTRG FFC7 RBOOT 0080 OC1M5 0020 DEL 007F OC1M6 0040 XCOORD 23B7 PVILLOP 00F8 VFLAG 0002 OC1M7 0080 TCNTL 100F SPSR 1029 DEQ 226B BPROT 1035 RCKB 0008 RE 0004 LPERIOD 0005 TOC1 1016 R5T5 0020 TOC2 1018 FUNC_SET 0020 TOC3 101A ERASE 0004 TOC4 101C Symbol Table F:\chicken\timertest2.asm PAGE 28 TOC5 101E C_CURSOR 0002 INPUT FFAC CLEAR_DISP 20F7 LALARM 0009 PAUSE 2279 PACNT 1027 AEQ 2265 RS 001E OUT2BSP FFC1 R2T2 0004 JPAIE 00CA RES0 1001 OUT1BYT FFBB ROW 0008 RES1 1006 RES2 1037 RES3 1038 RES4 103E IRQE 0020 INVB 0001 ROW2_START 0040 T0 0002 T1 0004 SPCR 1028 SI 000F WAKE 0008 PVCLM 00FE JSWI 00F4 BYTE 0010 INF 23EB ESC 001B SO 000E T8 0040 BF 0080 OUTPUT FFAF NUL 0000 EELAT 0002 TIC1 1010 READ_LOC 2038 TIC2 1012 TIC3 1014 TIC4 101E CME 0008 CGRAM_ADDRSET 0040 TC 0040 REGIX 225E REGIY 2260 TE 0008 BS 0008 INITDEV FFA9 NFLAG 0008 MYSUB 240D MSG1 23EE ADJUST_DELAY 2451 MSG2 23F5 ADDRSIZE 0002 SPDR 102A