Abstract
To accelerate the speed of iterative computation for the existing SHA-256 algorithm, using 7-3-2 array compressor is proposed to reduce the critical path delay in this paper. The frequency of the proposed scheme is 1.7 times higher than other VLSI implementations under the same process. In addition, the paper designs a new universal architecture for implementing SHA-2 algorithms. The design is synthesized with the slow library of Synopsys Design Compiler in SMIC 0.18 ¿m CMOS process. Its function has been verified sufficiently on FPGA. Furthermore, compared with the existing SHA-256 core, the results of the ASIC synthesis and FPGA verification are more preferable. This design is convenient to implant into SoC and embedded system with the versatile architecture and high clock frequency.
