Current Research Projects
This page lists the presently-active research projects that I am involved in.
There is a widespread misconception that simulating quantum computers on classical ones requires exponential memory/storage space, when actually it only requires space that is at most linear in the number of (bounded-width) gate operations in the quantum circuit being simulated; this fact has been known since the early days of quantum complexity theory. To illustrate this point, we developed such a simulator in C++. Gee, that was easy; ho hum. Next?
This represents my own long-term research programme to more thoroughly understand the fundamental limits on information processing that are imposed by the laws of physics, with an aim towards gaining insights to help guide the design and development of new types of nanoelectronic devices and circuit technologies that are specifically engineered so as to approach the fundamental physical limits of computing as closely as is feasible.
This in an ongoing collaboration led by Erik DeBenedictis of the Scalable Computing Systems department in the Computation, Computers, Information, and Mathematics (CCIM) center at Sandia National Labs. Erik has an interest in developing a roadmap for supercomputing that will allow DOE’s computing capabilities to continue increasing exponentially over the next 10-20 years and beyond. It is becoming increasingly widely accepted that, due to excessive power consumption, conventional (meaning irreversible, non-energy-recovering) computers will be unable to continue meeting the ever-higher computational requirements of new supercomputing applications beyond a 10-20 year timeframe. Reversible computing (RC) provides a potential path to take future high-performance computing (HPC) beyond the thermodynamic performance limits of conventional computing. However, determining whether RC can be made practical requires detailed investigation of potential new nanoelectronic device technologies (for example, quantum dot cellular automata) that might offer better device-level performance characteristics than ordinary FET transistors, as well as new resonant clocking schemes based on transmission lines and MEMS elements for driving adiabatic logic transitions. This project has been funded through a series of small contracts from Sandia.
Reversible computing in adiabatic CMOS technology can potentially outperform conventional irreversible CMOS for ultra-low-power applications, if sufficiently high-quality resonant clock distribution mechanisms are available for energy recovery. In this project at the ECE department in the FAMU-FSU College of Engineering, we are investigating resonant clocking technologies including IBM/Columbia’s inductor-based resonant H-trees, as well as Multigig Inc.’s transmission-line-based “Rotary Clock.” We are designing aggressively power-optimized conventional and fully-adiabatic versions of some basic sequential circuits (such as counters), and are planning to carry out detailed simulations of these circuits, when driven by various clock generators, with the goal of demonstrating that well-designed adibatic CMOS circuits, driven by resonant clocks, can compute with better overall system-level energy-efficiency (including clock dissipation) than even well-optimized irreversible CMOS circuits driven by resonant clocks.
In this project, being carried out in the multi-university High-performance Computing & Simulation (HCS) laboratory (a distributed facility operated jointly with the University of Florida), we are planning to develop and simulate protocols and systems for providing fault-tolerant distributed storage protocols based on iSCSI over P2P virtual networks.
This is another project of the HCS lab. It is investigating the development of fault-tolerant distributed network and storage techniques to support large-scale database applications specifically.
Additional projects are always pending.
Last edited on or after 3/25/2013