*================================================================ * FILE: fibonacci.asm * DESCRIPTION: Fibonaccy test program for the URISC processor model. * Register use: * r[0] = iport * r[1] = -1 * r[2-5] = temp * r[6-8] = fn,fn+1,fn+2 * r[9] = loop counter * r[15] = oport *================================================================ .global _EXIT .text ********* dst-=src, PC=? ********* Initialize the fn values L00: URISC r[6], r[6], +1 * fn=0 URISC r[7], r[7], +1 * r[7]=0 URISC r[7], r[1], +1 * fn+1=1 URISC r[9], r[9], +1 * loop-counter=0 *********** fn+2=fn+fn+1 L01: URISC r[2], r[2], +1 * r[2]=0 URISC r[2], r[6], +1 * r[2]=-fn URISC r[2], r[7], +1 * r[2]=-fn-fn+1 URISC r[8], r[8], +1 * r[8]=0 URISC r[8], r[2], +1 * fn+2=-(-fn-fn+1) *********** if loop counter++ >= iport => done URISC r[2], r[2], +1 * r[2]=0 URISC r[2], r[0], +1 * r[2]=-iport URISC r[3], r[3], +1 * r[3]=0 URISC r[3], r[2], +1 * r[3]=iport ************ inc iport for loop test ************ URISC r[3], r[1], +1 * r[3]++ URISC r[9], r[1], +1 * loop-counter+=1 URISC r[3], r[9], @L02 * done if iport