FROM:                                   Dr. U. Meyer-Baese

SUBJECT:                             URISC and ERISC supporting Information

ACKNOLEGMENT:            This material is based upon work supported by CoWare, Altera and Xilinx. Thanks for the provided hardware and software under the University programs. Any opinions, findings, and conclusions or recommendations expressed in this webpage are those of the authors and do not necessarily reflect the views of the sponsors.

 

This directory contains the software example source code and some simulation results of the URSIC and ERISC processor using Quartus web 6.0 and Xilinx ISE 9.2 as described in an upcoming papers.

 

Programming file for download to the Nexys and DE2 boards:

 

URISC

URISC

URISC

ERISC

ERISC

ERISC

Nexys:

IO

FIBONACCY

FACTORIAL

IO

FIBONACCY

FACTORIAL

DE2:

IO

FIBONACCY

FACTORIAL

IO

FIBONACCY

FACTORIAL

 

PDF files for the simulation results for URISC and ERISC and be downloaded.

 

Assembler software source code:

URSIC

 

IO

 

 

 

FIBONACCY

FACTORIAL

ERISC

ONE

IO

ALU

LOOP

DMTEST

FIBONACCY

FACTORIAL

 

 

 

RELATED PUBLICATIONS*

 

 

U. Meyer-Baese, G. Botella, S. Mookherjee, E. Castillo, A. García,  (in press) “Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology” Microprocessors and Microsystems, pp. 11, 2011

 

U. Meyer-Baese, G. Botella, E. Castillo, A. García,  “A Balanced HW/SW Teaching Approach for Embedded Microprocessors” International Journal of Engineering Education, Vol 26, No. 3, pp. 584–592, 2010.

 

Uwe Meyer-Baese, A. Vera, S. Rao, K. Lenk, M. Pattichis, “FPGA Wavelet Processor Design using Language for Instruction-set Architectures (LISA),” Proc. SPIE Int. Soc. Opt. Eng., April 2007, Vol. 6576, pp. 65760U-1-12. DOWNLOAD PDF HERE

 

A. Vera, A. Vera, U. Meyer-Baese and M. Pattichis, “An FPGA based rapid prototyping platform for wavelet coprocessors,” Proc. SPIE Int. Soc. Opt. Eng., April 2007, Vol. 6576, pp. 657615-1-10. DOWNLOAD PDF HERE

 

U. Meyer-Baese, D. Sunkara, E. Castillo, and A. García, “Custom Instruction Set NIOS-based OFDM Processor for FPGAs,” Proc. SPIE Int. Soc. Opt. Eng., April 2006, Vol. 6248, pp. 6248U-1-10. DOWNLOAD PDF HERE

 

 

Presenter in bold

 

*Copyright 2006, 2007 Society of Photo-Optical Instrumentation Engineers. These papers were published in SPIE conference Proceedings and are made available as an electronic reprint (preprint) with permission of SPIE. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.